Papers by Keyword: Epitaxial Growth

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Authors: Lin Dong, Guo Sheng Sun, Jun Yu, Guo Guo Yan, Wan Shun Zhao, Lei Wang, Xin He Zhang, Xi Guang Li, Zhan Guo Wang
Abstract: We present our recent results on of 10 × 100 mm 4H-SiC epitaxy by a warm-wall planetary reactor at a growth rate of 10 μm/h. The epilayers grown by this high-throughput reactor show specular surfaces and good uniformities of thickness and doping. The intra-wafer and wafer-to-wafer thickness uniformities are 2.0% and 0.5%, respectively, while intra-wafer and wafer-to-wafer doping uniformities are 14.0% and 3.4%, respectively. The obtained surface RMS roughness is 0.2 nm. These results suggest that this 10 × 100 mm warm-wall planetary reactor provides very promising prospect on the mass production of 4H-SiC epilayers, which will further promote the development of SiC-based electronic devices.
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Authors: Kazukuni Hara, Hiroaki Fujibayashi, Yuuichi Takeuchi, Shoichiro Omae
Abstract: In this work, we have developed a selective embedded epitaxial growth process on 150-mm-diameter wafer by vertical type hot wall CVD reactor with the aim to realize the all-epitaxial 4H-SiC MOSFETs [1, 2, 3, 4, 5]. We found that at elevated temperature and adding HCl, the epitaxial growth rate at the bottom of trench is greatly enhanced compare to growth on the mesa top. And we obtain high growth rate 7.6μm/h at trench bottom on 150mm-diameter-wafer uniformly with high speed rotation (1000rpm).
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Authors: Wei Ji, Peter M. Lofgren, Christer Hallin, Chun-Yuan Gu
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Authors: Kazukuni Hara, Masami Naito, Hiroaki Fujibayashi, Atsuya Akiba, Yuuichi Takeuchi, Olga Milikofu, Tomomi Kozu
Abstract: In this report we were able to successfully identify and localize in 3D 3C and 6H foreign polytypes and stress in the embedded epilayer by high resolution 3D Raman spectroscopy, that were otherwise invisible under the microscope or SEM, in non-contact and non-destructive way. Stripe patterned deep trenches with aspect ratio about 2 (depth=3.0μm; width=1.5μm) were formed on 4H-SiC substrate by ICP. The epitaxial layer was embedded in these trenches by SiC CVD. Poly type defects and stress in the embedded epilayer were mapped by curve-fitting of spectra obtained from Raman measurement of the embedded SiC epilayer. The location of the foreign polytypes and the stress inside the stripe pattern allows speculating on the origin of the defects and correlating it to the manufacturing process.
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Authors: Kazutoshi Kojima, Tetsuo Takahashi, Yuuki Ishida, Satoshi Kuroda, Hajime Okumura, Kazuo Arai
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Authors: Hidekazu Tsuchida, Isaho Kamata, Tamotsu Jikimoto, Toshiyuki Miyanagi, Kunikaza Izumi
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Authors: Takashi Aigo, M. Sawamura, Tatsuo Fujimoto, Masakazu Katsuno, Hirokatsu Yashiro, Hiroshi Tsuge, Masashi Nakabayashi, Taizo Hoshino, Noboru Ohtani
Abstract: 4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates made it possible to decrease the substrate temperature and specular surface morphologies were realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of 1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of 1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at 1500°C and it was verified that a high quality metal-semiconductor interface was formed on the epitaxial layer.
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Authors: Birgit Kallinger, Bernd Thomas, Patrick Berwian, Jochen Friedrich, Gerd Trachta, Arnd Dietrich Weber
Abstract: Homoepitaxial growth on 4° off-axis substrates with different off-cut directions, i.e. [11-20] and [1-100], was investigated using a commercial CVD reactor. The characteristics of the growth process on substrates with different off-cut directions were determined with respect to applicable C/Si ratio, growth rate and n- and p-type doping range. Stable step flow growth was achieved over a broad range of C/Si ratio at growth rates ~ 15 µm/h in both cases. The n-type doping level of epilayers can be controlled at least in the range from 5  1014 cm-3 to 3  1017 cm-3 on both types of substrates. Highly p-type epilayers with p = 2  1019 cm-3 can also be grown on [1-100] off-cut substrates. Hence, the growth process for standard substrates was successfully transferred to [1-100] off-cut substrates resulting in epilayers with similar doping levels. The dislocation content of the grown epilayers was investigated by means of defect selective etching (DSE) in molten KOH. For both off-cut directions of the substrates, similar densities of threading edge dislocations (TED), threading screw dislocations (TSD) and basal plane dislocations (BPD) were found in the epilayers. Epilayers with very low BPD density can be grown on both kinds of substrates. The remaining BPDs in epilayers are inclined along the off-cut direction of the substrate. The surface morphology and roughness was investigated by atomic force microscopy (AFM). The epilayers grown on [1-100] off-cut substrates are smoother than those on standard substrates.
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Authors: Bharat Krishnan, Joseph Neil Merrett, Galyna Melnychuk, Yaroslav Koshka
Abstract: In this work, the benefits of the low-temperature halo-carbon epitaxial growth at 1300oC to form anodes of 4H-SiC PiN diodes were investigated. Regular-temperature epitaxial growth was used to form an 8.6 μm-thick n-type drift region with net donor concentration of 6.45x1015 cm-3. Trimethylaluminum doping, in situ during blanket low-temperature halo-carbon epitaxial growth, was used to form heavily doped p-type layers. Forward I-V characteristics measured from diodes having different anode areas indicated that the new epitaxial growth technique provides anodes with low values of the series resistance, even without contact annealing. At room temperature, a 100 μm-diameter diode had a forward voltage of 3.75 V at 1000A/cm² before annealing and 3.23 V after annealing for 2 min at 750°C. The reverse breakdown voltage was more than 680 V (on average) in the devices without edge termination or surface passivation.
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