Papers by Keyword: Etch Rate

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Authors: Mark Robson, Kristin A. Fletcher, Ping Jiang, Michael B. Korzenski, A. Upham, T. Haigh Jr., Thomas J.C. Hsieh
Abstract: In semiconductor processing, test wafers are used as particle monitors, film thickness monitors for deposition and oxide growth measurements, dry/wet etch rate monitors, CMP monitors, as well as characterizing new and existing equipment and processes. Depending on fab size and capacity, monthly test wafer usage can be tens of thousands or more. Due to the ever increasing demand for silicon between the IC and solar markets and the high cost of 300mm wafers, chip manufacturers are increasing their efforts to reduce overall spending on silicon - currently by far the largest non equipment related cost [1]. One approach taken by many chip makers is the concept of extending the usable life of test wafers by re-using them as many times as possible through a reclaim process.
Authors: Michael B. Korzenski, D.D. Bernhard, T.H. Baum, Koichiro Saga, Hitoshi Kuniyasu, Takeshi Hattori
Authors: Masayuki Wada, H. Takahashi, James Snow, Rita Vos, Thierry Conard, Paul W. Mertens, H. Shirakawa
Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.
Authors: Dennis H. van Dorp, Daniel Cuypers, Sophia Arnauts, Paul W. Mertens, Stefan de Gendt
Abstract: Compound semiconductors based on group III and V elements of the periodic system have high charge carrier mobility and are, therefore, candidates for channel material in future CMOS devices [1]. In order to design wet chemical solutions that lead to appropriate surface pre-conditioning and allow for nanoscale processing and minimal substrate loss, a thorough understanding of the interactions between the substrate and the chemical solutions is needed and the basic etching mechanisms needs to be resolved. The focus of this research is on InP in acidic solutions. ESH aspects are also considered.
Authors: W. Storm, H.A. Gerber, G.-F. Hohl, M. Naujok, R. Schmolke
Authors: Gyu Hyun Kim, Soon Young Park, Seung Seok Pyo, Ji Hye Han, Jung Nam Kim, Kee Joon Oh, Choon Kun Ryu, Yong Soo Choi, Noh Jung Kwak, Sung Ki Park
Abstract: As a design rule of memory devices is scaled down to sub-100 nm, shallow trench isolation (STI) technology is faced with gap-filling problem in case of CVD oxide and O3-TEOS oxide processes. To overcome the gap-filling problem, a perhydropolysilazane (PHPS) based spin-on dielectric (SOD) has been implemented for nanoscale devices because of self-planarization and excellent gap-filling property [1]. However, the stability of the SOD has been concerned about because it has relatively softer and more porous than conventional HDP oxide. In this paper, we report the effect of wet oxidant treatment on the stability of the SOD for STI gap-filling.
Authors: Sonja Sioncke, David P. Brunco, Marc Meuris, Olivier Uwamahoro, Jan Van Steenbergen, Evi Vrancken, Marc M. Heyns
Abstract: The Si transistor has dominated the semiconductor industry for decades. However, to fulfill the demands of Moore’s law, the Si transistor has been pushed to its physical limits. Introducing new materials with higher intrinsic carrier mobility is one way to solve this problem. Ge, GaAs and InGaAs are known for their high mobilities and are therefore suitable candidates for replacing Si as a channel material. However, introduction of new materials raises new issues. For Si processing, several steps such as cleaning, etching and stripping are based on wet treatments. The knowledge of etch rates of the semiconductor material is of great importance. In this paper, etch rates of Ge, GaAs and InGaAs in several chemical solutions are studied. A comparison of the etch rates is made between the materials.
Authors: Ji Hyun Jeong, Bong Kyun Kang, Min Su Kim, Hong Seong Sohn, Ahmed A. Busnaina, Jin Goo Park
Abstract: In the semiconductor wafer cleaning, ammonium hydroxide based APM (ammonium peroxide mixture) has been widely used to remove particles and organic contaminants [. However as the film thickness and line width of semiconductor structure scales down rapidly, the material losses by etching reaction of alkaline chemicals can cause serious problem in yield loss due to electric failure. The presence of H2O2 could enhance the material loss on silicon wafer. Very dilute alkaline chemicals might be of interest since it could minimize any possible ionic contamination or chemical residues from chemicals as long as we control the surface roughness and particle removal efficiency. Also the characterization of these very dilute alkaline chemicals will be very useful for particle removal in gas dissolved DI water.
Authors: Ismail Kashkoush, Lewis Liu, Nick Yialamas, R. Novak
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