Papers by Keyword: Hole Traps

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Authors: Patrick Fiorenza, Filippo Giannazzo, Alessia Frazzetto, Alfio Guarnera, Mario Saggio, Fabrizio Roccaforte
Abstract: This paper reports on the conduction mechanisms through the gate oxide and trapping effects at SiO2/4H-SiC interfaces in MOS-based devices subjected to post deposition annealing in N2O. The phenomena were studied by temperature dependent current–voltage measurements. The analysis of both n and p-MOS capacitors and of n-channel MOSFETs operating in the “gate-controlled-diode” configuration revealed an anomalous hole conduction behaviour through the SiO2/4H-SiC interface, with the onset of current conduction moving towards more negative values during subsequent voltage sweeps. The observed gate current instabilities upon subsequent voltage sweeps were deeply investigated by temperature dependent cyclic gate current measurements. The results were explained by the charge-discharge mechanism of hole traps in the oxide.
Authors: Yoshihito Katsu, Takuji Hosoi, Yuichiro Nanen, Tsunenobu Kimoto, Takayoshi Shimura, Heiji Watanabe
Abstract: We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.
Authors: S. Scharf, M. Schmidt, D. Bräunig
Authors: L. Storasta, F.H.C. Carlsson, S.G. Sridhara, Boleslaw Formanek, Peder Bergman, Anders Hallén, Erik Janzén
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