Papers by Keyword: IP Core

Paper TitlePage

Authors: Hong Wei Tang
Abstract: This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily.
1848
Authors: Bao Shan You, Kai Feng Liu, Feng Lian Zeng, Li Ying Pei
Abstract: The new generation of Field Programmable Gate Array (FPGA) technology enables to embed a processor to construct a System on a Programmable Chip( SoPC). A stepper motion control IC for X-Y table using SoPC technology is proposed in this thesis. The proposed motion control IC contains two modules. One module performs the functions of schedule and logic control. Due to the need of complicated control algorithm, it is implemented by software using Nios II embedded processor. The other module performs the functions of interpolation, acceleration and deceleration. Due to the need of high performance, this module is implemented by Programmable Logic Device (PLD) in FPGA. The use of SoPC technology can make the motion control IC of X-Y table more compact, high performance and low cost .
67
Authors: Xu You Li, Na Zhang
Abstract: The sway motion of ships follows sine law. Therefore, it needs high dynamic performance of fiber optic gyroscope (FOG) to meet the serious working environment. A new test method was introduced to make reasonable assessment on the dynamic performance of FOG. The principle of this new test method was that the sine wave provided by the IP core in FPGA was superimposed on the digital ladder to simulate the input signal of sway motion. It could be proved that the serial of sine signal, which was generated by this method, was equivalent to the external input signal. Moreover, the dynamic error model of FOG was established to provide the theory of dynamic test. The results of dynamic test of FOG indicated that the dynamic error did not have divergent trends, the system parameters set was reasonable and the FOG system was stable. It also can be seen that dynamic error of FOG was increased with the increasing of sine wave amplitude, which was accord with the actual situation. The new dynamic test method of FOG was verified.
245
Authors: Shu Wen Zheng, Guang Hui Cai, H.W. Wang, G.Y. Zhang
Abstract: This paper introduces the basic principle of Viterbi code in OFDM system and a new implementation method based on FPGA, on and timing circuit are validated by using of EDA tools Quartus II. The new method is that the Viterbi decoding module is improved,which makes the design of the whole decoding structure can be improved and solves the compatibility problem among the modules. Finally, the simulation results is given and demonstrates that a good Viterbi code can be achieved by using FPGA in OFDM system, which can save the cost, shorten the designing cycle , and is convenient to speed up the listing of products, occupy less hardware resources, and comply with the development trend of modern communication.
399
Authors: Cheng Chen, Qian Huang, Yan Yan Yu, Wen Long Li, Jun Yang
Abstract: This paper analyzed the principle of the two-dimensional FFT algorithm, and adopted the time domain extracted base 2D-FFT algorithm and CORDIC to achieve a one-dimensional FFT IP core in Quartus II platform, then used this IP core matrix transposition module to structure 2D-FFT core processing unit desired. In SOPC system, we adopted custom components and IP core packaging technology and adding the integration of the module. Completed the design of SOPC system, which was simulated and downloaded to the development board for verification and the test results were compared to the Matlab operation results. The simulation and test results showed that this design had a simple hardware structure, high throughput, high stability and a good prospect.
1030
Authors: Gui Gen Zeng, Jiang Zhe Ren
Abstract: As a Basic Transforming Operation between Time Field and Frequency Field, FFT Has Been Widely Used in Detection, Telecommunication, Signal Processing, Multimedia Communication Etc. the Implementation of the FFT Algorithms on FPGA Is Always the Hot Research Spots. in Order to Overcome the Shortcomings on the FPGA Resource Reusability Used in FFT Algorithm, this Article Discusses a New Configurable and High Efficient FFT/IFFT Soft-core Solution. the FFT/IFFT Soft-core Adopts Radix-22 Algorithm and Single-Path Delay Feedback (SDF) Pipeline Structure. its Configurable Factors Include: FFT/IFFT, FFT Points (2n, [3,12] ), Fixed-point Bit Width, Clock Delay of Complex Multiplier. the Design Takes FPGA Chip Stratix II EP2S130F780C4 as Hardware Platform, and the Complete Simulation and Synthesis Is Taken. the Maximum Operating Frequency Is up to 306.30MHz. if 300MHz Clock Frequency Used, 4096-point FFT Could Be Realized in 26.73us, and the Consumption of Memory Resources Is only 148Kbit. Compared with Altera FFT IP-core, Our FFT/IFFT Soft-core Has a Little Bit Longer Computing Time (0.6%). however, the LE Resource Consumption Is only 79% of Altera FFT IP-core. Platform, and the Complete Simulation and Synthesis Is Taken. the Maximum Operating Frequency Is up to 306.30MHz. if 300MHz Clock Frequency Used, 4096-point FFT Could Be Realized in 26.73us, and the Consumption of Memory Resources Is only 148Kbit. Compared with Altera FFT IP-core, Our FFT/IFFT Soft-core Has a Little Bit Longer Computing Time (0.6%). however, the LE Resource Consumption Is only 79% of Altera FFT IP-core.
2901
Authors: Xia Qing Tang, Xiang Liu, Jun Qiang Gao, Bo Lin
Abstract: Since FPGA processing data, the presence of fixed-point processing accuracy is not high, and IP Core floating point unit and there are some problems in the use of design risk. Based on the improved floating point unit and program optimization algorithm is designed to achieve single-precision floating-point add / subtract, multiply, and divide operations operator. IP Core for floating-point unit design and FPGA development software provides comparative results: both the maximum clock frequency and latency basically unchanged, while the former occupies less hardware resources, to complete a plus / minus, multiply, divide computation time required for the former than the latter were reduced by 46%, 37% and 57%. The program is downloaded to the FPGA chip to get the same results with the simulation results verify the correctness and feasibility of the design.
1465
Authors: Qun Xiu Yu, Shou Ming Zhang, Chao Wang, Li Zhi Xie
Abstract: In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.
621
Authors: Guang Hui Cai, Shu Wen Zheng, Ping Li, Chuan Liang
Abstract: This paper introduces the basic principle of RS codes in OFDM system and the design method of 16 shift registers, finite field multiplicators and adders, on and timing circuit are validated by using of EDA tools Quartus II. Finally, the simulation results is given and demonstrates that a good channel encoding and decoding can be achieved by using FPGA in OFDM system, which can save the cost, shorten the designing cycle , and is convenient to speed up the listing of products, occupy less hardware resources, and comply with the development trend of modern communication.
2619
Authors: Ya Li Chen, Li Kun Zheng, Zhe Ying Li
Abstract: A series of portable mass storage devices are arising due to the effective support from USB interface for its special features, such as easy to use, a high transfer speed and low price. 8051_USB IP core is to achieve data acquisition and efficient data transfer to PC. The abstract of USB Protocol is introduced firstly. Then the design and verification of 8051_USB IP core are discussed in detail. Modules of 8051_USB protocol controller are designed with Verilog HDL. The design is simulated with Modelsim.
387
Showing 1 to 10 of 21 Paper Titles