Papers by Keyword: Ion Implantation

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Authors: Giorgio Lulli, Roberta Nipoti
Abstract: In this work under-mask penetration of Al+ ions implanted in 4H-SiC is investigated by computer simulation based on the Monte-Carlo binary collision approximation (MC–BCA). Results indicate that a small fraction of ions, implanted normal to a (0001) 4H-SiC wafer (8° off-axis towards the {11-20}), is scattered and become channeled in the <1120> directions perpendicular to the <0001> axis. Due to this phenomenon, doped regions with concentration ≤ 10− 4 of the peak value, may extend laterally for a few µm below the edge of a SiO2 mask.
421
Authors: Y. Kobayashi, Shinsuke Harada, Hiroshi Ishimori, Shinji Takasu, Takahito Kojima, Keiko Ariyoshi, Mitsuru Sometani, Junji Senzaki, Manabu Takei, Yasunori Tanaka, Hajime Okumura
Abstract: A 3.3 kV trench MOSFET with double-trench structure was demonstrated. The deep buried p-base regions were fabricated using tilt angle ion implantation into the sidewalls of the trench contacts. The distance between the trench gate and trench contact was determined through simulation, in order to optimize the trade-off between on-resistance (RonA) and the electrical field in the oxide (Eox). A tapered trench was located in the connective area between the edge termination and the active area, in order to maintain breakdown voltage. We achieved a RonA of 10.3 mWcm2 and a breakdown voltage of 3843 V and the maximum Eox at breakdown voltage was estimated to be 3.2 MV/cm.
974
Authors: Nicolò Piluso, Maria Ausilia di Stefano, Simona Lorenti, Francesco La Via
Abstract: 4H-SiC defects evolution after thermal processes has been evaluated. Different annealing temperatures have been used to decrease the defect density of epitaxial layer (as stacking faults) and recover the damage occurred after ion implantation. The propagation of defects has been detected by Photoluminescence tool and monitored during the thermal processes. The results show that implants do not affect the surface roughness and how a preliminary annealing process, before ion implantation step, can be useful in order to reduce the SFs density. It shown the effect of tuned thermal process. A kind of defect, generated by implant and subsequent annealing, can be removed by an appropriate thermal budget, while others can increase. A fine tuning of thermal process parameters, temperature and timing, is useful to recover the crystallographic quality of the epilayer and increase the yield of the power device.
181
Authors: Jeffery B. Fedison, Chris S. Cowen, Jerome L. Garrett, E.T. Downey, James W. Kretchmer, R.L. Klinger, H.C. Peters, Jesse B. Tucker, Kevin Matocha, L.B. Rowland, Steve Arthur
Abstract: Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).
1265
Authors: Alexander M. Ivanov, Evgenia V. Kalinina, Nikita B. Strokan, Alexander A. Lebedev
Abstract: The spectrometric characteristics of detectors based on 4H-SiC films with ion-doped p+–n junctions in a temperature range from 25 to 375 °C have been studied. The experiments with 5.8-MeV α-particles in a high-temperature chamber were performed. The interference factors of the detectors operation in a mode of spectrometry are established. The energy resolution of 1.35% is received. An increase of the efficiency of the diffusion–drift charge transport with increasing temperature has been observed. The last is explained by an increase in the diffusion length of minority carriers.
849
Authors: T. Paskova, E. Valcheva, Ivan G. Ivanov, Rositza Yakimova, Susan Savage, Nils Nordell, Chris I. Harris
741
Authors: Mihai Lazar, Christophe Raynaud, Dominique Planson, Marie Laure Locatelli, K. Isoird, Laurent Ottaviani, Jean-Pierre Chante, Roberta Nipoti, Antonella Poggi, G.C. Cardinali
827
Authors: S. Peripolli, Marie France Beaufort, David Babonneau, Sophie Rousselet, P.F.P. Fichtner, L. Amaral, Erwan Oliviero, Jean François Barbot, S.E. Donnelly
Abstract: In the present work, we report on the effects of the implantation temperature on the formation of bubbles and extended defects in Ne+-implanted Si(001) substrates. The implantations were performed at 50 keV to a fluence of 5x1016 cm-2, for distinct implantation temperatures within the 250°C≤Ti≤800°C interval. The samples are investigated using a combination of cross-sectional and plan-view Transmission Electron Microscopy (TEM) observations and Grazing Incidence Small-Angle X-ray Scattering (GISAXS)measurements. In comparison with similar He implants, we demonstrate that the Ne implants can lead to the formation of a much denser bubble system.
357
Authors: Kenshiro Nakashima, Yasuo Okuyama, Shinji Ando, Osamu Eryu, Koji Abe, H. Yokoi, T. Oshima
1427
Authors: Paul J. Timans
Abstract: Radiant energy sources enable rapid and controllable thermal processing of wafers with closed-loop control of wafer temperature. However the use of energy sources that are not in thermal equilibrium with the wafers makes the heating process sensitive to the optical properties of the wafers. In particular, patterns on wafer surfaces can cause temperature non-uniformity at length scales where lateral thermal conduction cannot smooth out the effect. Such “pattern effects” are even more significant for advanced processing techniques like millisecond annealing and pulsed laser annealing, because of the extremely large heating powers employed. The issue of pattern effects was recognized early on in the development of radiant heating technology, but has recently become a critical issue for process control. Despite the challenges, many counter-measures can be deployed to minimize pattern effects, including modifications to the wafer design, changes in processing recipe and equipment configuration. Such solutions have enabled the use of radiant heating for even the most demanding device fabrication applications.
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