Papers by Keyword: PiN

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Authors: Anant K. Agarwal
Abstract: The last three years have seen a rapid growth of 600 V and 1200 V SiC Schottky diodes primarily in the Power Factor Correction (PFC) circuits. The next logical step is introduction of a SiC MOSFET to not only further improve the power density and efficiency of the PFC circuits but also to enable the entry of all SiC power modules in Pulse Width Modulated (PWM) based power converters such as motor control in 600-1200 V range. The combination of SiC MOSFET and Schottky diodes will offer 60-80% lower losses in most low voltage applications at normal operating temperatures (< 200°C) where no significant improvements in packaging are required. This will cover most commercial applications with the exception of those having to function under extreme environment (>200°C) such as applications in automotive, aerospace and oil/gas exploration. For these high temperature applications, a case can be made for 600 - 2000 V Bipolar Junction Transistors (BJTs) and PiN diodes provided we do our homework on high temperature packaging. A number of interesting device related problems persist in bipolar devices such as forward voltage increase in PiN diodes and current gain degradation in BJTs. For very high voltage (>10 kV) applications such as those found in utilities (Transmission and Distribution), Large Drives and Traction, a case can be made for >10 kV PiN diodes, IGBTs, Thyristors and GTOs. While IGBTs will be restricted to <200°C junction temperature, the PiN diodes, Thyristors and GTOs may be operated at >250°C junction temperature provided that the high temperature, high voltage packaging issues are also addressed. Significant progress has been made in the development of the p-channel IGBTs and GTOs. The main issues seem to be the VF degradation due to stacking fault formation and improvement of minority carrier life-time.
Authors: Satoshi Tanimoto, Kenichi Ueoka, Takaya Fujita, Sawa Araki, Kazu Kojima, Toshiharu Makino, Satoshi Yamasaki
Abstract: A new rectifier, called SPND or SNPD (Schottky-PN or -NP junction diode) and inherently showing low on-resistance and unipolar operation, was experimentally demonstrated for the first time on 4H-SiC. It is structured with an n or a p region of very low doping that is sandwiched and completely depleted between a Schottky junction and a one-sided PN junction. Either electrons or holes, but not both, contribute to the current conduction process. Clear and sharp rectifying properties are observed over the entire range of applied voltage.
Authors: A. Walsh, B. C. Baliga, Peter D. Hodgson
Authors: Ulrike Grossner, Francesco Moscatelli, Roberta Nipoti
Abstract: Two families of Al+ implanted vertical p+in diodes that have been processed all by identical steps except the post implantation annealing one have been characterized with current voltage measurements from -100 to +5V at different temperatures. Analysis of the static forward current voltage characteristics shows two different ideality factor regions, which are distinct for each family. The reverse current voltage characteristics reveals corresponding two different activation energies. These are assumed to be correlated to the Z1/2 defect for the one case and another one with an activation energy of 0.25eV.
Authors: Uwe Zimmermann, John Österman, Jie Zhang, Anne Henry, Anders Hallén
Authors: Ranbir Singh, Kenneth G. Irvine, Jim Richmond, John W. Palmour
Authors: Victor Veliadis, M. Snook, H. Hearne, B. Nechay, S. Woodruff, C. Lavoie, C. Kirby, Eugene A. Imhoff, J. White, Stuart M. Davis
Abstract: The multiple-zone junction termination extension (MJTE) is a widely used SiC edge termination technique that reduces sensitivity to implantation dose variations. It is typically implemented in multiple lithography and implantation events. To reduce process complexity, cycle time, and cost, a single photolithography/implantation (P/I) MJTE technique was developed and diodes with 3-zone and 120-zone JTEs were fabricated on the same wafer. Here, the process tolerance of the single (P/I) MJTE technique is evaluated by performing CCD monitored blocking voltage measurements on diodes from the same wafer with the 3-zone and 120-zone single (P/I) JTE. The 3-zone JTE diodes exhibited catastrophic localized avalanches at the interface between the 2nd and 3rd zones due to abrupt zone transitions. Diodes with the smooth transitioning 120-zone JTE exhibited no CCD detectable avalanches in their JTE regions up to the testing limit of 12 kV. Under thick dielectric (deposited for on-wafer diode interconnection), diodes with the single P/I 3-zone JTE failed due to significant loss of high-voltage capability, while their 120-zone JTE diode counterparts were minimally affected. Overall, the single (P/I) 120-zone JTE provides a process-tolerant and robust single P/I edge termination at no additional fabrication labor.
Authors: Megan Snook, Ty McNutt, Chris Kirby, Harold Hearne, Victor Veliadis, Bettina Nechay, Sharon Woodruff, R.S. Howell, Joseph White, Stuart Davis
Abstract: The multi-zone junction termination extension (MJTE) is a widely used edge termination technique for achieving high voltage SiC devices. It is commonly implemented with multiple lithography and implantation events. In order to reduce process complexity, cycle time, and cost, a single photolithography and single implant MJTE technique has been successfully developed. The method utilizes a pattern of finely graduated oxide windows that filter the implant dose and create a graded MJTE in a single implant and single photolithography step. Based on this technique, 6 kV / 0.09 cm2 PiN diodes were fabricated utilizing a 120-zone single-implant JTE design. This novel single-implant MJTE design captures 93% of the ideal breakdown voltage and has comparable performance and yield to a baseline three implant process.
Authors: Bharat Krishnan, Rooban Venkatesh K.G. Thirumalai, Siva Prasad Kotamraju, Joseph Neil Merrett, Yaroslav Koshka
Abstract: Vanadium doping from SiCl4 source during epitaxial growth with chlorinated C and Si precursors was investigated as a mean of achieving compensated and semi-insulating epitaxial 4H-SiC layers for device applications. Thin epilayers were grown at 1450°C with a growth rate of ~6 μm/h. Experiments at 1600°C resulted in the growth rates ranging from 60 to 90 µm/h producing epilayers with thickness above 30 µm. V concentrations up to about 1017cm-3 were found safe for achieving defect-free epilayer surface morphology, however certain degradation of the crystalline quality was detected by XRD at V concentrations as low as 3-5x1015 cm-3. Controllable compensation of nitrogen donors with V acceptors provided low-doped and semi-insulating epitaxial layers. Mesa isolated PiN diodes with V-acceptor-compensated n- epilayers used as drift regions showed qualitatively normal forward- and reverse-bias behavior.
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