Papers by Keyword: Threshold Voltage

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Authors: Matthieu Florentin, Mihaela Alexandru, Aurore Constant, Bernd Schmidt, Philippe Godignon
Abstract: This work presents the 10 MeV protons irradiation effects on 4H-SiC MOSFETs at different fluences. MOSFETs main electrical parameters, such as the channel mobility (µEFF), threshold voltage (VTH), transconductance (gm) and subthreshold current, were analyzed using the time bias stress instability (BSI) technique. Applying this method allowed us to study the effect of carriers interaction with generated interface traps, whether in the bulk or at the interface. Improvements, such as VTH stabilization in time and a significant increase of the µEFF at high fluencies, have been noticed. We assume that this behavior is connected with the atomic diffusion from the SiO2/SiC interface, towards the epilayer during proton irradiation. These atoms, in majority Nitrogen, may create other bonds by occupying various vacancies coming from Silicon and Carbon’s dangling bond. Therefore, by enhancing the passivated Carbon atoms number, we show that high irradiation proton could be a way to improve the SiO2/SiC interface quality.
Authors: Shinsuke Harada, Y. Kobayashi, A. Kinoshita, N. Ohse, Takahito Kojima, M. Iwaya, Hiromu Shiomi, Hidenori Kitai, Shinya Kyogoku, Keiko Ariyoshi, Yasuhiko Onishi, Hiroshi Kimura
Abstract: A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.
Authors: J. Kaido, Tsunenobu Kimoto, Jun Suda, Hiroyuki Matsunami
Authors: Akio Takatsuka, Yasunori Tanaka, Koji Yano, Tsutomu Yatsuo, Kazuo Arai
Abstract: In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.
Authors: Jian Liu, Li Li, X.H. Zhang
Abstract: A physics-based threshold voltage model is proposed, according to the electrostatics distribution in Si body of FinFET which is obtained by 2-D numerical simulation. Threshold voltage of FinFET calculated from the model is matched with results of numerical simulation. Influences of polysilicon gate doping concentration, Si body doping concentration, the width and height of Si body and the gate oxide thickness on threshold voltage were investigated. As results,Si body doping concentration, gate doping concentration and the width of Si body have been found to be the most important parameters for the design of threshold voltage of FinFET-like devices.
Authors: Kevin M. Speer, Philip G. Neudeck, Mehran Mehregany
Abstract: The SiC vacuum field-effect transistor (VacFET) was first reported in 2010 as a diagnostic tool for characterizing the fundamental properties of the inverted SiC semiconductor surface without confounding issues associated with thermal oxidation. In this paper, interface state densities are extracted from measurements of threshold voltage instability on a SiC VacFET and a SiC MOSFET. It is shown that removing the oxide can reduce the interface state density by more than 70%.
Authors: Xiao Feng Zhuang, Qing Kai Zeng, Bing Ren, Zhen Hua Wang, Yue Lu Zhang, Li Ya Shen, Mei Bi, Jian Huang, Ke Tang, Ling Yun Shi, Yi Ben Xia, Lin Jun Wang
Abstract: In this paper, the threshold voltage of diamond film-based metal-semiconductor field effect transistors (MESFETs) has been simulated using Silvaco TCAD tools. The drain current (Id) versus gate voltage (Vg) relationship, and the distribution of acceptors in diamond surface conduction layer were also investigated. From the simulation results, it was found that the gate length contributed the most to the threshold voltage, while the doping depth almost had no impact on the threshold voltage value.
Authors: R. Ramakrishna Rao, S. Balaji, Kevin Matocha, Vinayak Tilak
Abstract: In 4H silicon carbide MOSFETs, threshold voltage varies with temperature. It is believed that this is caused by trapping of inversion electrons at high density of interface-traps (Dit) present at the SiC/SiO2 interface in 4H-SiC MOSFETs. In this work, we present an approach to model the interface trap density as a function of temperature that includes the effect of band gap narrowing. Using the temperature dependent trap charge density, we can estimate the variation of mobile inversion layer charge density, which in turn, explains the threshold voltage behavior with temperature in 4H-SiC MOSFETs.
Authors: Can Zhu, Rong Bin Hu
Abstract: For the first time, the capacitive non-linearity is considered and calibrated. Based on the traditional bootstrapped switch, a cell is added to eliminate the first-order capacitive non-linearity. The measurement shows that the sampling and holding circuit using the improved bootstrapped switch can achieve a SFDR of 86dB with respect to 76dB for the traditional one.
Authors: Fauziyah Salehuddin, Anis Suhaila Mohd Zain, Niza Mohd Idris, Ahmad Kamal Mat Yamin, Afifah Maheran Abdul Hamid, Ibrahim Ahmad, P. Susthitha Menon
Abstract: In this research, orthogonal array of L27 in Taguchi Method was used to optimize the process parameters (control factors) variation in 45nm n-channel device with considering the interaction effect. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the device. There are only five process parameters (control factors) were varied for 3 levels to performed 27 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of Vth for every row of experiment. In this study, nominal-the-best characteristic was used in an effort to minimize the variance of Vth. The results show that the Vth values have least variance and percent different from the target value (0.287V) for this device is 1.42% (0.293V). This value is closer with International Technology Roadmap for Semiconductor (ITRS) prediction.
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