Papers by Keyword: 4H-SiC

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Authors: E. Rauls, Z. Hajnal, Peter Deák, Thomas Frauenheim
Authors: Guo Sheng Sun, Yong Mei Zhao, Liang Wang, Lei Wang, Wan Shun Zhao, Xing Fang Liu, Gang Ji, Yi Ping Zeng
Abstract: The in-situ p-type doping of 4H-SiC grown on off-oriented (0001) 4H-SiC substrates was performed with trimethylaluminum (TMA) and/or diborane (B2H6) as the dopants. The incorporations of Al and B atoms and their memory effects and the electrical properties of p-type 4H-SiC epilayers were characterized by secondary ion mass spectroscopy (SIMS) and Hall effect measurements, respectively. Both Al- and B-doped 4H-SiC epilayers were p-type conduction. It was shown that the profiles of the incorporated boron and aluminum concentration were in agreement with the designed TMA and B2H6 flow rate diagrams. The maximum hole concentration for the Al doped 4H-SiC was 3.52×1020 cm-3 with Hall mobility of about 1 cm2/Vs and resistivity of 1.6~2.2×10-2 Wcm. The heavily boron-doped 4H-SiC samples were also obtained with B2H6 gas flow rate of 5 sccm, yielding values of 0.328 Wcm for resistivity, 5.3×1018 cm-3 for hole carrier concentration, and 7 cm2/Vs for hole mobility. The doping efficiency of Al in SiC is larger than that of B. The memory effects of Al and B were investigated in undoped 4H-SiC by using SIMS measurement after a few run of doped 4H-SiC growth. It was clearly shown that the memory effect of Al is stronger than that of B. It is suggested that p-type 4H-SiC growth should be carried out in a separate reactor, especially for Al doping, in order to avoid the join contamination on the subsequent n-type growth. 4H-SiC PiN diodes were fabricated by using heavily B doped epilayers. Preliminary results of PiN diodes with blocking voltage of 300 V and forward voltage drop of 3.0 V were obtained.
Authors: Yu Yang, Jian Qiu Guo, Balaji Raghothamachar, Michael Dudley, Swetlana Weit, Andreas N. Danilewsky, Patrick J. McNally, Brian R. Tanner
Abstract: We present in-situ observations of the dynamical operation of multiple double-ended Frank-Read dislocation sources in a PVT-grown 4H-SiC wafer under thermal gradient stresses. The nucleation of these sources is facilitated by a specific configuration consisting of one basal plane dislocation (BPD) segment pinned by two threading edge dislocations (TEDs). This configuration is formed during PVT crystal growth by deflection of TEDs on to the basal planes by macrosteps and re-deflection of resulting BPDs back into TEDs. Under the influence of thermal gradient stresses induced by heating inside a double ellipsoidal mirror furnace, the pinned BPD segment glides and activates dislocation multiplication by the double Frank-Read source mechanism. A more intricate mechanism of swapping of TED pinning points between Frank-Read sources lying on same basal plane is identified, enabling one dislocation loop to effectively “pass through” the other dislocations on same basal plane.
Authors: Ki Jeong Han, B. Jayant Baliga, Woong Je Sung
Abstract: This paper presents a 1.2kV-rated 4H-SiC Split-Gate power MOSFET (SG-MOSFET) with superior high frequency figures-of-merit (HF-FOM). Electrical characteristics including reverse transfer capacitance and gate-to-drain charge are measured from fabricated devices on a 6-inch SiC wafer, demonstrating excellent performance. Compared to the conventional MOSFETs, the SG-MOSFET provides about 7x smaller HF-FOM [RonxCgd] and 2x smaller HF-FOM [RonxQgd] with improved reverse transfer capacitance and gate-to-drain charge.
Authors: Hiroshi Kono, Takuma Suzuki, Kazuto Takao, Masaru Furukawa, Makoto Mizukami, Chiharu Ota, Shinsuke Harada, Junji Senzaki, Kenji Fukuda, Takashi Shinohe
Abstract: 1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.
Authors: Lin Dong, Guo Sheng Sun, Jun Yu, Guo Guo Yan, Wan Shun Zhao, Lei Wang, Xin He Zhang, Xi Guang Li, Zhan Guo Wang
Abstract: We present our recent results on of 10 × 100 mm 4H-SiC epitaxy by a warm-wall planetary reactor at a growth rate of 10 μm/h. The epilayers grown by this high-throughput reactor show specular surfaces and good uniformities of thickness and doping. The intra-wafer and wafer-to-wafer thickness uniformities are 2.0% and 0.5%, respectively, while intra-wafer and wafer-to-wafer doping uniformities are 14.0% and 3.4%, respectively. The obtained surface RMS roughness is 0.2 nm. These results suggest that this 10 × 100 mm warm-wall planetary reactor provides very promising prospect on the mass production of 4H-SiC epilayers, which will further promote the development of SiC-based electronic devices.
Authors: Takeo Yamamoto, Jun Kojima, Takeshi Endo, Eiichi Okuno, Toshio Sakakibara, Shoichi Onda
Abstract: 4H-SiC SBDs have been developed by many researchers and commercialized for power application devices in recent years. At present time, the issues of an SiC-SBD are lower on-state current and a relatively larger-leakage current at the reverse bias than Si-PN diodes. A JBS (Junction Barrier Schottky) diode was proposed as a structure to realize a lower leakage current. We simulated the electrical characteristics of JBS diodes, where the Schottky electrode was made of molybdenum in order to optimize its performance. We fabricated JBS diodes based on the simulation with a diameter of 3.9mm (11.9 mm2). The JBS diode has a lower threshold voltage of 0.45 V, a large forward current of 40 A at Vf = 2.5V and a high breakdown voltage of 1660 V. Furthermore, the leakage current at 1200 V was remarkably low (Ir = 20 nA).
Authors: Dethard Peters, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Daniel Kueck, Romain Esteve
Abstract: A detailed analysis of the typical static and dynamic performance of the new developed Infineon 1200V CoolSiCTM MOSFET is shown which is designed for an on-resistance of 45 mΩ. In order to be compatible to various standard gate drivers the gate voltage range is designed for-5 V in off-state and +15 V in on-state. Long term gate oxide life time tests reveal that the extrinsic failure evolution follows the linear E-model which allows a confident prediction of the failure rate within the life time of the device of 0.2 ppm in 20 years under specified use condition.
Authors: Yasunori Tanaka, Koji Yano, Mitsuo Okamoto, Akio Takatsuka, Kazuo Arai, Tsutomu Yatsuo
Abstract: We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.
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