Papers by Keyword: ALD

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Authors: B. Brennan, S. McDonnell, D. Zhernokletov, H. Dong, C.L. Hinkle, J. Kim, R.M. Wallace
Abstract: Atomic layer deposition (ALD) of high dielectric constant (high-k) materials for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology has now resulted in the investigation of transistors incorporating alternative channel materials, such as III-V compounds. The control of the interfacial chemistry between a high-k dielectric and III-V materials presents a formidable challenge compared to that surmounted by Si-based technologies. The bonding configuration is obviously more complicated for a compound semiconductor, and thus an enhanced propensity to form interfacial defects is anticipated, as well as the need for surface passivation methods to mitigate such defects. In this work, we outline our recent results using in-situ methods to study the ALD high-k/III-V interface. We begin by briefly summarizing our results for III-As compounds, and then further discuss recent work on III-P and III-Sb compounds. While arsenides are under consideration for nMOS devices, antimonides are of interest for pMOS. InP is under consideration for quantum well channel MOS structures in order to serve as a better nMOS channel interface. In all cases, a high-k dielectric interface is employed to limit off-state tunneling current leakage.
Authors: Muhammad I. Idris, Nick G. Wright, Alton B. Horsfall
Abstract: 3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.
Authors: Markku Leskela, Emma Salmi, Mikko Ritala
Abstract: This paper reviews the use of Atomic Layer Deposition (ALD) in protective coatings. Because of the growth principle ALD allows the deposition of dense conformal films on substrates of different size and shape. Recently, ALD has received increasingly interest in deposition of protective coatings. In protective coatings oxides are the most common materials and especially Al, Ti, and Ta oxides have been applied. The use of nanolaminates enables improving the protection properties. Since ALD films are pinhole-free and often thin they are used to protect against moisture, radiation, out-gassing but not often against corrosion of metals. Very good moisture barriers are obtained with thin ALD oxide layers on polymers and cardboard. This property is also very attractive in encapsulation of OLEDs. In studies of energy technology materials protection of electrodes in Li-ion batteries, fuel cells and supercapacitors by ALD has been reported and significant improvement in the stability has been achieved. Yet another area is protection of silver jewelry from tarnishing by a thin oxide layer. In traditional corrosion protection of metals ALD films have proven to be useful in tailoring of interfaces and sealing of defects in coatings made by other techniques.
Authors: Jing Hua Xia, David M. Martin, Sethu Saveda Suvanam, Carl Mikael Zetterling, Mikael Östling
Abstract: LaxHfyO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N2O ambient. The result shows that high quality LaxHfyO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.
Authors: Seckson Sukhasena, P. Pungboon Pansila
Abstract: The computational prediction of the surface adsorption in atomic layer deposition of gallium oxide by using trimethylgallium (TMG) is investigated. One dimer of Si (100)(2×1) is used as the substrate. The hydroxyl radicals are used to produce the absorption sites for the TMG adsorbed surface as OH–Si–Si–OH surface species. Two sites adsorption of the TMG on the surface are predicted. The geometry, vibrational frequency, and free energy of –OH adsorption sites and TMG adsorption are calculated by Gaussian 09 package by using standard B3LYP method. The results showed that TMG is possible to adsorb on silicon dimer with two sites adsorption. The geometry and vibrational frequencies are also reported in this paper.
Authors: Muhammad I. Idris, Nick G. Wright, Alton B. Horsfall
Abstract: This paper reports on the effect of forming gas annealing on the C-V characteristics and stability of Al2O3/SiC MOS capacitors deposited by atomic layer deposition, (ALD). C-V and I-V measurements were performed to assess the quality of the Al2O3 layer and the Al2O3/SiC interface. In comparison to as-deposited sample, the post oxide annealing (POA) in forming gas at high temperatures has improved the stability of C-V characteristic and the properties at the interface of Al2O3/SiC capacitors. However, the oxide capacitance and oxide breakdown electric field degrade with increased annealing temperature. The results provide indications to improve the performance of Al2O3/SiCcapacitors 4H-SiC devices by optimizing the annealing temperature.
Authors: Toby Hopf, Konstantin Vassilevski, Enrique Escobedo-Cousin, Peter King, Nicholas G. Wright, Anthony G. O’Neill, Alton B. Horsfall, Jonathan Goss, George Wells, Michael Hunt
Abstract: Top-gated field-effect transistors have been created from bilayer epitaxial graphene samples that were grown on SiC substrates by a vacuum sublimation approach. A high-quality dielectric layer of Al2O3 was grown by atomic layer deposition to function as the gate oxide, with an e-beam evaporated seed layer utilized to promote uniform growth of Al2O3 over the graphene. Electrical characterization has been performed on these devices, and temperature-dependent measurements yielded a rise in the maximum transconductance and a significant shifting of the Dirac point as the operating temperature of the transistors was increased.
Authors: Xiang Yu Yang, Bong Mook Lee, Veena Misra
Abstract: In this work, we have developed a novel gate stack to enhance the mobility of Si face (0001) 4H-SiC lateral MOSFETs while maintaining a high threshold voltage. The gate dielectric consists a thin lanthanum silicate layer at SiC/dielectric interface and SiO2 deposited by atomic layer deposition. MOSFETs using this interface engineering technique show a peak field effect mobility of 133.5 cm2/Vs while maintaining a positive threshold voltage of above 3V. The interface state density measured on MOS capacitor with lanthanum silicate interfacial layers is reduced compared to the capacitors without the silicate. It is shown that the presence of the lanthanum at the interface reduces the formation of a lower quality SiOx interfacial layer typically formed at the SiC surface during typical high temperature anneals. This better quality interfacial layer produces a sharp SiC/dielectric interface, which is confirmed by cross section Z-contrast STEM images.
Authors: Min Seok Kang, Bong Mook Lee, Veena Misra
Abstract: This study reports the electrical characteristics and reliability of the atomic layer deposited SiO2 on the 4H-SiC substrate. By controlling the thickness of SiO2 in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO2 dielectrics as well as reduction in interface state density at SiC/SiO2 interface.
Authors: W. Melitz, J.B. Clemens, J. Shen, E.A. Chagarov, S. Lee, J.S. Lee, J.E. Royer, M. Holland, S. Bentley, D. McIntyre, I. Thayne, R. Droopad, A.C. Kummel
Abstract: The megasonic cleaning efficiency is evaluated as a function of the angle of incidence of acoustic waves on a Si wafer. Acoustic Schlichting streaming alone is not able to remove nanoparticles smaller than 400 nm. It is shown that oscillating or collapsing behavior of bubbles are responsible for removing nanoparticles smaller than 400 nm during a cleaning process with ultrasound. Optimal particle removal efficiency is obtained around the angle of acoustic transmission of the silicon wafer.
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