Papers by Keyword: Basal Plane Dislocation (BPD)

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Authors: Akio Shima, Haruka Shimizu, Yuki Mori, Masakazu Sagawa, Kumiko Konishi, Ryusei Fujita, Takashi Ishigaki, Naoki Tega, Keisuke Kobayashi, Shintaroh Sato, Yasuhiro Shimamoto
Abstract: We investigated improvement ways of to overcome these reliability issues in a 3.3 kV 4H-SiC DMOSFET. JFET doping with (i) narrow width and (ii) deeper depth than that of the p-well region successfully reduced the electric field in the gate insulator and the on-voltage simultaneously. We achieved a low Ron of 26 mΩcm2 at a Vg of +15 V and 150 °C. And highly reliable chips of 0.1 Fit were also achieved both at a positive and negative gate bias of +15 V/ -8 V with MTTF of intrinsic lifetime over 20 years at 3 MV/cm. BTI characterstics both in positive and negative biases also proved reliability over 20 years. The body diode showed stable behavior under forward current operation which is suitable for an external diode-less power module.
Authors: Pierre Brosselard, Nicolas Camara, Jawad ul Hassan, Xavier Jordá, Peder Bergman, Josep Montserrat, José Millan
Abstract: An innovative process has been developed by Linköping University to prepare the 4HSiC substrate surface before epitaxial growth. The processed PiN diodes have been characterized in forward and reverse mode at different temperature. The larger diodes (2.56 mm2) have a very low leakage current around 20 nA @ 500V for temperatures up to 300°C. A performant yield (68%) was obtained on these larger diodes have a breakdown voltage superior to 500V. Electroluminescence characteristics have been done on these devices and they show that there is no generation of Stacking Faults during the bipolar conduction.
Authors: Yuan Bu, Hiroyuki Yoshimoto, Kumiko Konishi, Akio Shima, Yasuhiro Shimamoto
Abstract: We designed, fabricated and evaluated 6.5 kV SiC PiN diodes. In order to suppress process-induced basal plane dislocation (BPD) in SiC PiN diodes, we improved the fabrication processes. The Ir-Vr measurements showed that the breakdown voltage was over 9 kV at room temperature (25 °C). The leakage currents (Ileak) at 6.5 kV are as low as 5.9×10-6 mA/cm2 (25 °C) and 9.7×10-5 mA/cm2 (150 °C). The maximum recovery loss among our switching test results was 6.7 mJ at 150 °C, 60 A. Moreover, the diodes fabricated on BPD-free area are very stable during applying 20 A current for 8~1000 h. Photoluminescence (PL) observation and KOH etching indicated that no BPD generated during improved fabrication processes.
Authors: Keiji Wada, Takemi Terao, Hironori Itoh, Tsutomu Hori, Hideyuki Doi, Masaki Furumai, Tatsuya Tanabe
Abstract: Epitaxial growth of 4H-SiC on 150 mm wafers has been investigated using experimental results and numerical simulations toward the goal of BPDs reduction and doping uniformity control in the epitaxial layer. We have reported analyses of the temperature distribution dependence of the doping uniformity and BPDs propagations on the 3 x 150 mm multi-wafer CVD epitaxial growth. By optimizing epitaxial growth conditions, we have demonstrated an excellent doping and thickness uniformity and a 99.9% BPD free region, simultaneously.
Authors: Robert E. Stahlbush, Rachael L. Myers-Ward, Brenda L. VanMil, D. Kurt Gaskill, Charles R. Eddy
Abstract: The recently developed technique of UVPL imaging has been used to track the path of basal plane dislocations (BPDs) in SiC epitaxial layers. The glide of BPDs during epitaxial growth has been observed and the role of this glide in forming half-loop arrays has been examined. The ability to track the path of BPDs through the epitaxy has made it possible to develop a BPD reduction process for epitaxy grown on 8° offcut wafers, which uses an in situ growth interrupt and has achieved a BPD reduction of > 98%. The images also provide insight into the strong BPD reduction that typically occurs in epitaxy grown on 4° offcut wafers.
Authors: Seo Young Ha, William M. Vetter, Michael Dudley, Marek Skowronski
Authors: Krzysztof Grasza, Emil Tymicki, Jaroslaw Kisielewski
Abstract: Silicon carbide crystals were grown from the vapor. Improvement of the quality of the central part of the crystal was achieved by optimization of the geometry of the source material. Active thermal interaction of the source material and the crystallization front made possible an effective programming of the shape and morphology of the crystal. Termination of micropipes on microfacets formed on the crystallization front during growth was observed.
Authors: I. Brazil, Patrick J. McNally, N. Ren, L. O'Reilly, A. Danilewsky, T.O. Tuomi, A. Lankinen, A. Säynätjaki, R. Simon, Stanislav I. Soloviev, L.B. Rowland, Peter M. Sandvik
Abstract: We present herein a first comparative analysis of the quality of 50 mm and 75 mm diameter SiC wafers, purchased directly from vendors across the world, types including the most widely available configurations. Large Area White Beam Synchrotron Back Reflection X-Ray Topography was used to analyse selected ~1cm2 regions at various locations on up to 10 different bulk SiC wafers. The study concentrated particularly on the density and distribution of threading screw dislocations (TSDs). We also examined all wafers for basal plane dislocation (BPDs) densities and distributions. Alarmingly large variation in wafer quality was observed. TSD densities vary from a minimum of 0 cm-2 (in a-plane material) to values as large as over 2,000 cm-2 on some n-type 4H-SiC wafers. TSD densities on individual wafers can also vary by similar magnitudes, e.g. 500cm-2 to 2,500 cm-2 on two regions only 2 cm apart on a 50 mm diameter wafer. Computer-based image process analysis was used to present a statistical analysis of the distributions of defects. For example algorithms created in MATLAB®, Image Processing Toolbox, isolated possible TSD locations allowing rapid counting to be performed. These counts were confirmed by manual counting of selected unmodified images.
Authors: Masayuki Sasaki, Kentaro Tamura, Hideki Sako, Makoto Kitabatake, Kazutoshi Kojima, Hirohumi Matsuhata
Abstract: Surface roughening regions running like scratches are often observed locally after epitaxy film grown on a very flat 4H-SiC wafer surfaces. We investigated generation mechanism of such roughening surface by using X-ray topography and confocal optical microscopy. We found that lattice defects were often introduced during CMP at local regions, and those local regions cannot be recognized by optical microscopy, since very flat surface can be observed. By H2 etching which is preprocess of epitaxy film growth, those lattice defects are almost etched off, but local rough surface consists of pits and step bunching regions appear like scratches, and those local pits and surface roughening regions grew up to step bunching during epitaxy film growth.
Authors: Atsushi Tanaka, Naoyuki Kawabata, Masatoshi Tsujimura, Yukihiro Furukawa, Taizo Hoshino, Yoshinori Ueji, Kazuhiko Omote, Hirotaka Yamaguchi, Hirofumi Matsuhata, Kenji Fukuda
Abstract: In this study, we investigated the annealing temperature dependence of dislocation extension in an ion-implanted region of a 4H-silicon carbide (SiC) C-face epitaxial layer, revealing that a high temperature annealing led to dislocation formation. We also investigated the current-voltage (I-V) characteristics of a 4H-SiC PIN diode with and without these extended dislocations. We demonstrated that the forward biased I-V characteristics of samples with extended interfacial dislocations have a kink at lower current regions.
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