Papers by Keyword: Breakdown Voltage

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Authors: Heu Vang, Christophe Raynaud, Pierre Brosselard, Mihai Lazar, Pierre Cremillieu, Jean Louis Leclercq, Sigo Scharnholz, Dominique Planson, Jean-Pierre Chante
Abstract: Silicon carbide devices limitations often originate from the quality of the substrate material. Therefore it is interesting to investigate devices fabricated on alternative source materials. Currently, CREE is the world market leader of SiC wafers. Nowadays, some new companies begin to propose alternative material. The European manufacturer SiCrystal furnishes now some epiwafers for the fabrication of 1,2kV devices. In this paper we present 4H-SiC 1.2 kV pin diodes with a JTE termination realized on a SiCrystal epiwafer. The devices exhibit a blocking voltage of 1.2 kV, a current density of 420 and a specific differential series resistance of 4.4 m-⋅cm2. The yield of fabricated diodes with a breakdown voltage greater 600 V is superior to 75%.
Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.
Authors: Chaichana Suksamosorn, Kittipong Tonmitra, Amnart Suksri
Abstract: A common field distortion triggered spark gap utilizing geometric field enhancement at sharp edges usury operates in a cascade mode via the trigger electrode. A new trigger concept is propos this research allowing strong non-uniform electric field enhancement with output precision voltage by holding-off DC voltage ranging from 1 to 135 kV and direct breakdown between the two main electrodes. A test setup was designed to testing with four modes of operation as mode A, B, C and D to prove the feasibility on this concept. Were result experimental r the recommended mode of operation is mode A and mode D considered to be unsatisfied to most applications. The best results achieved by using the triggering with mode A at a wide precision designed breakdown voltage range 1-120kV with a minimum percentage ratio of Fire/Self-fire Voltage lower to 36-47%
Authors: Siddarth G. Sundaresan, Charles Sturdevant, Madhuri Marripelly, Eric Lieser, Ranbir Singh
Abstract: Sharp avalanche breakdown voltages of 12.9 kV are measured on PiN rectifiers fabricated on 100 µm thick, 3 x 1014 cm-3 doped n- epilayers grown on n+ 4H-SiC substrates. This equates to a record high 129 V/µm for a > 10 kV device. Optimized epilayer, device design and processing of the SiC PiN rectifiers result in a > 60% blocking yield at 10 kV, ultra-low on-state voltage drop and differential on-resistance of 3.75 V and 3.3 mΩ-cm2 at 100 A/cm2 respectively. Open circuit voltage decay (OCVD) measured carrier lifetimes in the range of 2-4 µs are obtained at room temperature, which increase to a record high 14 µs at 225 °C. Excellent stability of the forward bias characteristics within 10 mV is observed for a long-term forward biasing of the PiN rectifiers at 100 A/cm2. A PiN rectifier module consisting of five parallel large area 6.4 mm x 6.4 mm 10 kV PiN rectifiers is connected as a free-wheeling diode with a Si IGBT and 1100 V/100 A switching transients are recorded. Data on the current sharing capability of the PiN rectifiers is also presented.
Authors: Ranbir Singh, Stoyan Jeliazkov, Eric Lieser
Abstract: 1200 V-Class Super-High Current Gain Transistors or SJTs developed by GeneSiC are distinguished by low leakage currents of 2. Two-stage cascaded SJTs display a record high current gain of 3475. Results from detailed on-state, blocking, switching and reliability characterization of 1200 V-class 4 mm2 and 16 mm2 SiC SJTs are presented in this paper.
Authors: Yasunori Tanaka, Koji Yano, Mitsuo Okamoto, Akio Takatsuka, Kazuo Arai, Tsutomu Yatsuo
Abstract: We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.
Authors: Martin Domeij, Carina Zaring, Andrei O. Konstantinov, Muhammad Nawaz, Jan Olov Svedberg, Krister Gumaelius, Imre Keri, Anders Lindgren, Bo Hammarlund, Mikael Östling, Mats Reimark
Abstract: This paper reports large active area (15 mm2) 4H-SiC BJTs with a low VCESAT=0.6 V at IC=20 A (JC=133 A/cm2) and an open-base breakdown voltage BVCEO=2.3 kV at T=25 °C. The corresponding room temperature specific on-resistance RSP-ON=4.5 mΩcm2 is to the authors knowledge the lowest reported value for a large area SiC BJT blocking more than 2 kV. The on-state and blocking characteristics were analyzed by device simulation and found to be in good agreement with measurements. Fast switching with VCE rise- and fall-times in the range of 20-30 ns was demonstrated for a 6 A 1200 V rated SiC BJT. It was concluded that high dynamic base currents are essential for fast switching to charge the BJT parasitic base-collector capacitance. In addition, 10 μs short-circuit capability with VCE=800 V was shown for the 1200 V BJT.
Authors: Siddarth Sundaresan, Stoyan Jeliazkov, Ranbir Singh
Abstract: Large-area, 7.84 mm2 SiC DMOSFETs feature breakdown voltages of 4600 V, specific on-resistance of 17 mΩ-cm2 and gate threshold voltage of 2.4 V. The low on-resistance was enabled by an optimized MOS process that resulted in channel mobility as high as 27 cm2/Vs, and oxide breakdown fields in the 10-11 MV/cm range. The key device design and layout parameters were varied to examine the performance versus reliability trade-offs.
Authors: Geun Ho Song, Hyoung Wook Kim, Wook Bahng, Sang Cheol Kim, Nam Kyun Kim
Authors: Hidefumi Takaya, Jun Morimoto, Toshimasa Yamamoto, Jun Sakakibara, Yukihiko Watanabe, Narumasa Soejima, Kimimori Hamada
Abstract: A 4H-SiC trench MOSFET has been developed that features trench gates with a thick oxide layer on the bottoms of the trenches. The maximum electric field strength and gate-drain charge of this device are 46% and 38%, respectively lower than that of a conventional MOSFET. The drain-source breakdown voltage is 1400V and the specific on-resistance is 4.4mΩcm2 at a gate bias of 20V and a drain voltage of 2V.
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