Papers by Keyword: C-V

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Authors: A. Kakanakova-Georgieva, Rositza Yakimova, Jie Zhang, L. Storasta, Mikael Syväjärvi, Erik Janzén
259
Authors: Bellan Chandar Shekar, S. Sathish, B.T. Bhavyasree, B. Ranjith Kumar
Abstract: Poly methyl methacrylate (PMMA) thin films were prepared by fast dip coating technique (FDCT). Benzene was used as a solvent to prepare PMMA films for various time periods ranging from 60 sec. to 1 hour. The thickness of the coated films were measured by using an electronic thickness measuring instrument (Tesatronic-TTD-20), gravimetric method and cross checked by optical spectrophotometer. FTIR spectrum was used to identify the above said coated films. XRD spectra of as grown and films annealed at various temperatures indicated the amorphous nature. Surface morphology of the coated films was studied by scanning electron microscope (SEM). No pits and pin holes were found in the surface. Both as grown and annealed films showed smooth and amorphous structure. C-V behavior of the MISM structures with Aluminum/PMMA/p-Si/Aluminum has been studied. C-V behavior for various bias voltage range of - 20 V to +20 V was provided. As grown films showed a flat band voltage (VFB) shift towards the positive voltage where as annealed films showed a decrease in VFB shift and it moved towards the zero flat band voltage (VFB  0) value. The observed surface morphology, C-V behavior and thermal stability indicated that these films could be used as effective dielectric layer in FET applications.
309
Authors: D. Ziane, Jean Marie Bluet, Gérard Guillot, Phillippe Godignon, Josep Montserrat, R.R Ciechonski, Mikael Syväjärvi, Rositza Yakimova, L. Chen, Philip A. Mawby
1281
Authors: Niladri Pratap Maity, R.K. Thapa, S. Baishya
Abstract: In this paper different characteristic parameters using high-k dielectric materials in Metal Oxide Semiconductor (MOS) device have been compared from the theoretical and simulated Capacitance-Voltage (C-V) graphs. The simulation has been done using ATLAS device simulator. The agreement of the specified values while deriving and simulating and that extracted is excellent. Further, the extracted parameters for high-k dielectric materials show an inferior interfacial quality.
60
Authors: Gaetano Izzo, Grazia Litrico, Lucia Calcagno, Gaetano Foti, Francesco La Via
Abstract: The defects produced by irradiation with 7 MeV C+ induce a change in the electrical properties of 4H-SiC Schottky diodes. Capacitance-voltage and Current-voltage characteristics of the diodes fabricated in epilayers doped with different nitrogen concentrations were monitored before and after irradiation with different fluences. The Capacitance-voltage curves show free carrier compensation after low fluence irradiation and it was found that the reduction of carriers per ion induced vacancy increases with nitrogen content. The forward current-voltage characteristics of the diodes show an increase in the series resistance after irradiation. This change is mainly related to the high compensation occurring around the end of the ion range.
619
Authors: Filippo Fabbri, Francesco Moscatelli, Antonella Poggi, Roberta Nipoti, Anna Cavallini
Abstract: Capacitance versus Voltage (C-V) and Deep Level Transient Spectroscopy (DLTS) measurements of Al+ implanted p+n diodes with Al+ implanted Junction Termination Extension are here studied. These diodes present C-V characteristics like graded junction for low forward bias values, i.e. > 0.4 V , or like abrupt junctions for large reverse bias, i.e. between 0.4V and -10V. The depth range of the graded junction, computed by the capacitance values, is much larger than the simulated tail of the ion implanted Al+ profile. DLTS spectra have been measured both in injection and standard configuration and always show minority carrier traps in the temperature range 0-300K. Three are the minority carrier related peaks, one attributed to the Al acceptor and the others to the D and D1 defects. The depth distribution of these hole traps will be discussed with respect to the apparent carrier concentration, obtained by C-V analysis.
469
Authors: M.M. Sobolev, A.V. Gittsovich, S.G. Konnikov, I.V. Kochnev, B.S. Yavich
1547
Authors: A.R. Frederickson, P.J. Drevinsky
1403
Authors: Chong Mu Lee, Anna Park, Su Young Park, Min Woo Park
Abstract: Effects of the O2/Ar flow ratio in the reactive sputtering process and the annealing temperature on the structure and surface roughness of ZrO2 films and the electric properties of Pt/ZrO2/Si MOS capacitors in which the ZrO2 film was deposited by magnetron sputtering have been investigated. The optimum process parameters of the Pt/ZrO2/Si capacitor based on reactively sputtered- ZrO2 determined in such a way as the capacitance is maximized and the leakage current, the oxide charge, and the interface trap density are minimized is the O2/Ar flow ratio of 1.5 and the annealing temperature of 800°C
937
Authors: Li Hong Cheng, L. Yu, F. Yu, Z.Z. Lu, Xiang Fu Zhao, Ping Han, H. Zhao, Z.L. Xie, X.Q. Xiu, R. Zhang, Y.D. Zheng
Abstract: The Ge mole fraction (x) of Si1-xGex layer was described by the C-V technique for Schottkey contact of single heterojunction Si1-xGex/Si, whose structure profile can be characterized by SEM image and EDS. Then the strained Si cap layer was grown on the Si1-xGex/Si, and C-V technique was used to determine the carrier concentration and structure of double heterojunction Si/Si1-xGex/Si. The change of the structure between Si1-xGex/Si and Si/ Si1-xGex/Si was also observed by this method.
1568
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