Papers by Keyword: Epitaxial Layer

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Authors: Seo Young Ha, William M. Vetter, Michael Dudley, Marek Skowronski
443
Authors: Christian Hecht, Bernd Thomas, René A. Stein, Peter Friedrichs
Abstract: In this paper, we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system VP2000HW from Epigress with a capability of processing 7×3” or 6×100mm wafers per run in a new 100mm setup. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 6×100mm and 7×3” runs will be shown. Results on Schottky Barrier Diodes (SBD) processed in the multi-wafer system will be given. Furthermore, we show results for n- and p-type SiC homoepitaxial growth on 3”, 4° off-oriented substrates using a single-wafer hot-wall reactor VP508GFR from Epigress for the development of PiN-diodes with blocking voltages above 6.5 kV. Characteristics of n- and p-type epilayers and doping memory effects are discussed. 6.5 kV PiN-diodes were fabricated and electrically characterized. Results on reverse blocking behaviour, forward characteristics and drift stability will be presented.
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Authors: Xuan Zhang, Masahiro Nagano, Hidekazu Tsuchida
Abstract: Morphologies of basal plane dislocations (BPDs) in 4H-SiC epilayers doped with nitrogen or aluminum are explained in detail. While BPDs in low N-doped or Al-doped epilayers show the morphology of gliding dislocations responding to stresses, BPDs in highly N-doped (≥1.0×1018 cm-3) epilayers appear different. Some of them are parallel to [11-20] while others are straight and tilt from [11-20]. Tilt BPDs were also studied by TEM. Factors that relate to such morphology are discussed.
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Authors: V. Khomenkov, D. Bisello, M. Boscardin, Mara Bruzzi, A. Candelori, G.-F. Dalla Betta, A.P. Litovchenko, C. Piemonte, R. Rando, F. Ravotti, N. Zorzi
Abstract: Radiation hardness of silicon detectors based on thin epitaxial layer for the LHC upgrade was studied. No type inversion was observed after irradiation by 24 GeV protons in the fluence range (1.5–10)⋅1015 cm–2 due to overcompensating donor generation. After long-term annealing highly irradiated devices show decrease of effective doping concentration and then undergo type inversion. All mentioned means that thin epitaxial devices might be used for innermost layers of vertex detectors and need moderate cooling during beam off time. Properly chosen scenario might help to restore their working characteristics.
315
Authors: Mitsuhiro Kushibe, Johji Nishio, Ryosuke Iijima, Akira Miyasaka, Hirokuni Asamizu, Hidenori Kitai, Ryoji Kosugi, Shinsuke Harada, Kazutoshi Kojima
Abstract: Carrier lifetime in low carrier concentration 4H-SiC epitaxial layers grown on the C-face was enhanced by using carbon implantation and post annealing. The measured carrier lifetime increased with the thickness of the epitaxial layer and was 11.4 µs for the 150 µm thick epitaxial layer. The internal carrier lifetime was estimated as 21 µs from the dependence of the measured carrier lifetime on the epitaxial layer thickness. This value is almost comparable to the reported values of the internal carrier lifetime for the layers grown on the Si-face.
432
Authors: Bernd Thomas, Christian Hecht, René A. Stein, Peter Friedrichs
Abstract: The rapid market development for SiC-devices during the last years can be attributed particularly to the success in supplying high-quality SiC wafers and corresponding epitaxial layers. The device quality could be enhanced and the costs were reduced by enlarging the wafer size as well as by a significant progress in epitaxial growth of active layers by using multi-wafer CVD systems. In this paper we want to give an overview of CVD multi-wafer systems used for SiC growth in the past and today. We present recent results of SiC homoepitaxial growth using our multi-wafer hot-wall CVD system. This equipment exhibits a capacity of 5×3” wafers per run and can be upgraded to a 7×3” or 5×4” setup. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity of doping and thickness have been grown. Issues like reproducibility, drift of parameters and system stability over several runs will be discussed.
135
Authors: Michio Tajima, M. Tanaka, Norihiro Hoshino
597
Authors: E.M. Geyfman, V.V. Chibirkin, G.Yu. Kamentsev, N.A. Gartsev, N.M. Davydova, B.P. Surin
Abstract: 4H-SiC epitaxial films grown on 4H-SiC in CVD reactor VP508GFR are investigated using FTIR, X-Ray diffraction, C-V measurements, stylus profiler and DIC optical microscopy.
593
Authors: Keiko Masumoto, Sachiko Ito, Hideto Goto, Hirotaka Yamaguchi, Kentaro Tamura, Chiaki Kudou, Johji Nishio, Kazutoshi Kojima, Toshiyuki Ohno, Hajime Okumura
Abstract: We have investigated a conversion of basal plane dislocation (BPD) to threading edge dislocation (TED) in growth of epitaxial layers (epi-layers) on 4H-SiC vicinal substrates with an off-angle of 0.85° at low C/Si ratio of 0.7 by using deep KOH etching and X-ray topography observations. Deep KOH etching indicated that BPDs in the substrates converted to TEDs in the epi-layers. X-ray topography observations suggested that the conversion occurred during epitaxial growth when the thickness of epi-layers was less than 1.5 μm. We found that the conversion ratio obtained from counting deep KOH etch pits was over 99%.
99
Authors: Norihito Yabuki, Satoshi Torimi, Satoru Nogami, Makoto Kitabatake, Tadaaki Kaneko
Abstract: We propose the thermal chemical etching process for Silicon Carbide (SiC) under the Si-vapor ambient using Tantalum Carbide / metal Tantalum composite materials (TaC/Ta). In this process, the high-rate “Si-vapor etching” method is applied to the removal of the surface damage and the formation of epi-ready surface. Over 10μm of “Si-vapor etching” provides smooth surface without latent scratch and low stacking faults density as same as on the CMP after epitaxial growth, which are observed by confocal microscope with differential interference contrast (C-DIC) microscope and Photo-Luminescence (PL) imaging measurement. Furthermore, the low-rate Si-vapor etching method, “Si-vapor ambient annealing” is applied to post-implantation activation annealing process without conventional C-cap. “Si-vapor ambient annealing” provides lower sheet resistance and smoother surface than the C-cap annealing after very high temperature annealing up to 2000 °C.
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