Papers by Keyword: FET

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Authors: Yoshitaka Sugawara, Katsunori Asano, Daisuke Takayama, Sei Hyung Ryu, R. Singh, John W. Palmour, Toshihiko Hayashi
Authors: R.N. Gupta, H.R. Chang, E. Hanna, C. Bui
Authors: Jeff B. Casady, David C. Sheridan, Robin L. Kelley, Volodymyr Bondarenko, Andrew Ritenour
Abstract: Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.
Authors: H. Aoki, N. Komatsu, M. Honjo, K. Masumoto, C. Kimura, T. Sugino
Abstract: A gate insulator film with a wide bandgap and a high dielectric constants required to achieve high power field effect transistor (FET) using wide bandgap semiconductors such as SiC and diamond. We can achieve to suppress the gate leakage current and the charge shifts by using the AlSiO film. We found that the leakage current of Nitrogen-doped AlSiO film can be suppressed in high temperature region compared with AlSiO film. In addition, we attempted to study Yttrium aluminate (YAlO) and Lanthanum aluminate (LaAlO) as a gate insulator film. Since the Y (+3) and La(+3) have the same valence as Al (+3), it is expected that there is an advantage that Y, La doping generates less dangling bonds in the Al2O3 film. We can achieve to form aluminum based oxide film with higher dielectric constant by doping Lanthanoid atoms such as Y and La. The optimized YAlO and LaAlO films were applied to SiC-MIS structure. The Lanthanoid and Aluminum based oxide films can readily be applicable to wide bandgap semiconductor devices.
Authors: R.P. Mikalo, P. Hoffmann, D.R. Batchelor, Anita Lloyd Spetz, Ingemar Lundström, D. Schmeißer
Authors: M. Salina, Mohd Zainizan Sahdan, N.A. Yusoff, U.M. Noor, Mohamad Rusop
Abstract: Zinc oxide (ZnO) is a one of the most interesting compound semiconductors that received more attention during last few years due to its unique properties. Due to that, this study has been done to manipulate those properties to be used for FET applications. The ZnO thin film has been deposited using the thermal chemical vapor deposition. This is done in a double furnace, which vapored the ZnO powder at different temperature. The growth of the ZnO thin film has been observed using SEM and the electrical properties has been analyzed by using I-V probe station. This is done to study the diode characteristics of ZnO thin film to be used in FET applications.
Authors: Takuma Suzuki, Junji Senzaki, Tetsuo Hatakeyama, Kenji Fukuda, Takashi Shinohe, Kazuo Arai
Abstract: The channel mobility and oxide reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs) on 4H-SiC (0001) carbon face were investigated. The gate oxide was fabricated by using dry-oxidized film followed by pyrogenic reoxidation annealing (ROA). Significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. Furthermore, the field-effect inversion channel mobility (μFE) of MOSFETs fabricated by using pyrogenic ROA was as high as that of conventional 4H-SiC (0001) MOSFETs having the pyrogenic-oxidized gate oxide. It is suggested that the pyrogenic ROA of dry oxide as a method of gate oxide fabrication satisfies both channel mobility and oxide reliability on 4H-SiC (0001) carbon-face MOSFETs.
Authors: Konstantinos Rogdakis, Seoung Yong Lee, Dong Joo Kim, Sang Kwon Lee, Edwige Bano, Konstantinos Zekentes
Abstract: In this work, SiC nanowire (NW) FETs are prepared and their electrical measurements are presented. From the samples fabricated on the same substrate, various I-Vs shapes are obtained (linear, non linear symmetric, and asymmetric). With the assistance of simulation, we show that this is a result of different values of Schottky Barrier Heights (SBH) at Source (S) / Drain (D) contacts of FETs. An origin for this might be a non uniformity in annealing, NW doping level and high interface traps density (that pins the Fermi level) as well as the high sensitivity of the metal-NW contacts to local surface contaminations.
Authors: Valeriya Kilchytska, Joaquin Alvarado, Otilia Militaru, Guy Berger, Denis Flandre
Abstract: This work discusses the degradations caused by high-energy neutrons in advanced MOSFETs and compares them with damages created by γ-rays reviewing the original researches performed in our laboratory during last years [1-6]. Fully–depleted (FD) Silicon-on-Insulator (SOI) MOSFETs and Multiple-Gate (MuG) FETs with different geometries (notably gate lengths down to 50 nm) have been considered. The impact of radiation on device behavior has been addressed through the variation of threshold voltage (VT), subthreshold slope (S), transconductance maximum (Gmmax) and drain-induced barrier lowering (DIBL). First, it is shown that degradations caused by high-energy neutrons in FD SOI and MuG MOSFETs are largely similar to that caused by γ-rays with similar doses [1,3]. Second, it is revealed that, contrarily to their generally-believed immunity to irradiation [7, 8], very short-channel MuGFETs with thin gate oxide can become extremely sensitive to the total dose effect [2,3]. The possible reason is proposed. Third, a comparative investigation of high-energy neutrons effects on strained and non-strained devices demonstrates a clear difference in their response to high-energy neutrons exposure [6]. Finally, based on simulations and modeling of partially –depleted (PD) SOI CMOS D Flip-Flop, we show how radiation-induced oxide charge and interface states build-up can affect well-known tolerance of SOI devices to transient effects [4,5].
Authors: Neetu Prasad, Anita Kumari, P.K. Bhatnagar, P.C. Mathur
Abstract: In the present work, we report fabrication and electrical characterization of a back gated graphene field effect transistor (GFET). We have focused our study on the interfacial effect (graphene/SiO2) on the performance of the device. Hysteresis was observed in the drain conductance when measured with respect to dual gate sweep voltage, which increases with increasing sweeping voltage range. The conductance was observed to increase with increase in temperature but there was no reduction in the hysteresis. This proved that temperature annealing could improve the channel conductivity but not the interfacial effects. Further, a metal oxide semiconductor (MOS) device was fabricated with SLG inserted in between the metal and oxide layer and its capacitance-voltage (C-V) characteristics were studied. A small series capacitance (2.1 nF) was observed to be existing in series with the oxide capacitance (4.5 nF) which was attributed to the trap states at the interface of graphene and SiO layer. Also, the flat band voltage was not affected by the incorporation of graphene layer in the MOS device indicating no change in the work function of the metal gate (Cr/Au). This is an advantageous situation where graphene does not alter its work function also being impermeable, restricts the diffusion of metal particles through the SiO2.
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