Papers by Keyword: GTO

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Authors: Q. Jon Zhang, Anant K. Agarwal, Craig Capell, L. Cheng, Michael J. O'Loughlin, Albert A. Burk, John W. Palmour, Sergey L. Rumyantsev, T. Saxena, Michael E. Levinshtein, A. Ogunniyi, Heather O'Brien, Charles Scozzie
Abstract: In this paper, for the first time, we report 12 kV, 1 cm2 SiC GTOs demonstrated with a novel negative bevel termination, which improves the breakdown voltage by >3.5 kV compared to the conventional multiple-zone Junction Termination Extension (JTE). The significant improvement in the blocking voltage was attributed to the elimination of the electrical field crowding in the periphery of the mesa with conventional JTE termination. This new termination has been used in both electrically and optically triggered SiC GTOs. An ultrafast turn-on speed of 70 ns has been measured on 12 kV, 1 cm2 SiC light triggered GTOs.
Authors: Lin Cheng, Anant K. Agarwal, Craig Capell, Michael J. O'Loughlin, Khiem Lam, Jon Zhang, Jim Richmond, Al Burk, John W. Palmour, Aderinto Ogunniyi, Heather O’Brien, Charles Scozzie
Abstract: In this paper, we report our recently developed 1 cm2, 15 kV SiC p-GTO with an extremely low differential on-resistance (RON,diff) of 4.08 mΩ•cm2 at a high injection-current density (JAK) of 600 ~ 710 A/cm2. The 15 kV SiC p-GTO was built on a 120 μm, 2×1014/cm3 doped p-type SiC drift layer with a device active area of 0.521 cm2. Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the RON,diff at JAK of 600 ~ 710 A/cm2 decreased from 4.08 mΩ•cm2 at 20°C to 3.45 mΩ•cm2 at JAK of 600 ~ 680 A/cm2 at 200°C. The gate to cathode blocking voltage (VGK) was measured using a customized high-voltage test set-up. The leakage current at a VGK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.
Authors: Pierre Brosselard, Thierry Bouchet, Dominique Planson, Sigo Scharnholz, Gontran Pâques, Mihai Lazar, Christophe Raynaud, Jean-Pierre Chante, Emil Spahn
Abstract: Overcoming the physical limits of silicon, silicon carbide shows a high potential for making high voltage thyristors. After a simulation based optimization of the main thyristor parameters, including JTE protection and a SiO2 layer passivation, 4H-SiC GTO thyristors were realized and characterized. Designed for a theoretical blocking capability of nearly 6 kV, the electrical characterization of all device structures revealed a maximum blocking voltage of 3.5 kV. Comparing simulation and measurement suggests that a negative oxide charge density of ~ 2×1012 cm-2 causes the decrease in electrical strength.
Authors: Anant K. Agarwal
Abstract: The last three years have seen a rapid growth of 600 V and 1200 V SiC Schottky diodes primarily in the Power Factor Correction (PFC) circuits. The next logical step is introduction of a SiC MOSFET to not only further improve the power density and efficiency of the PFC circuits but also to enable the entry of all SiC power modules in Pulse Width Modulated (PWM) based power converters such as motor control in 600-1200 V range. The combination of SiC MOSFET and Schottky diodes will offer 60-80% lower losses in most low voltage applications at normal operating temperatures (< 200°C) where no significant improvements in packaging are required. This will cover most commercial applications with the exception of those having to function under extreme environment (>200°C) such as applications in automotive, aerospace and oil/gas exploration. For these high temperature applications, a case can be made for 600 - 2000 V Bipolar Junction Transistors (BJTs) and PiN diodes provided we do our homework on high temperature packaging. A number of interesting device related problems persist in bipolar devices such as forward voltage increase in PiN diodes and current gain degradation in BJTs. For very high voltage (>10 kV) applications such as those found in utilities (Transmission and Distribution), Large Drives and Traction, a case can be made for >10 kV PiN diodes, IGBTs, Thyristors and GTOs. While IGBTs will be restricted to <200°C junction temperature, the PiN diodes, Thyristors and GTOs may be operated at >250°C junction temperature provided that the high temperature, high voltage packaging issues are also addressed. Significant progress has been made in the development of the p-channel IGBTs and GTOs. The main issues seem to be the VF degradation due to stacking fault formation and improvement of minority carrier life-time.
Authors: Yoshitaka Sugawara
Abstract: To achieve large current capability in spite of present small SiC devices that are limited by various crystal defects, focus was placed on SiC GTO thyristor and SICGT have been developed as an advanced SiC GTO. SICGTs with current capability of 1.6-100 A and blocking voltage of 3-12.7 kV and a 3 phase PWM SICGT inverter with output power of 35 kVA have been successfully developed. Furthermore, application of the SiC inverter aimed to a load leveling system was demonstrated.
Authors: Sei Hyung Ryu, Daniel J. Lichtenwalner, Michael O'Loughlin, Edward van Brunt, Craig Capell, Charlotte Jonas, Yemane Lemma, Jon Q. Zhang, Jim Richmond, Albert Burk, Brett Hull, Matthew McCain, Shadi Sabri, Heather O'Brien, Aderinto Ogunniyi, Aivars J. Lelis, Jeff Casady, Dave Grider, Scott Allen, John W. Palmour
Abstract: An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO2, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O2 between amorphous SiO2 and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in VF over the 1300°C oxidized devices, without any impact on blocking characteristics.
Authors: Gontran Pâques, Sigo Scharnholz, Nicolas Dheilly, Dominique Planson, Rik W. De Doncker
Abstract: This paper presents results attained with SiC GTO thyristors terminated by a single step and a graded etched JTE. The comparison of both types of devices reveals no significant difference in the on-state and switching characteristics but a higher blocking capability of some thyristors with the latter kind of termination. The best devices showed a forward breakdown voltage of nearly 6 kV, which is a distinct progress as against previous results of thyristors with a graded etched JTE. Furthermore, such GTO thyristors have been characterized dynamically for the first time.
Authors: Anant K. Agarwal, Albert A. Burk, Robert Callanan, Craig Capell, Mrinal K. Das, Sarah K. Haney, Brett A. Hull, Charlotte Jonas, Michael J. O'Loughlin, Michael O`Neil, John W. Palmour, Adrian R. Powell, Jim Richmond, Sei Hyung Ryu, Robert E. Stahlbush, Joseph J. Sumakeris, Q. Jon Zhang
Abstract: In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.
Authors: Leonid Fursin, Frank Hoffmann, John Hostetler, Xue Qing Li, Matthew Fox, Petre Alexandrov, Mari Anne Gagliardi, Mark Holveck
Abstract: A growing demand for smart and flexible photovoltaic power conversion and pulsed-power systems is leading to rapid development and commercialization of medium voltage 6.5 - 24 kV, wide-bang gap rectifiers and switches. Conventional silicon bipolar switches are limited to roughly 8 kV breakdown voltages and scaling up the voltage rating requires very thick wafers presenting significant manufacturing challenges. Very thick drift layers of silicon devices also translate into a very high minority carrier charge injected during forward conduction for an efficient conductivity modulation, hence leading to an extremely slow switching speed and poor efficiency. In this paper USCi presents the development of 6.5 kV 4H-SiC gate-turn-off thyristors (GTOs) with multiple floating guard-ring edge termination, and describes their application in an AC-link grid-tied solar inverter system.
Authors: Anant K. Agarwal, Pavel A. Ivanov, Michael E. Levinshtein, John W. Palmour, Sergey L. Rumyantsev
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