Papers by Keyword: High-k

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Authors: B. Brennan, S. McDonnell, D. Zhernokletov, H. Dong, C.L. Hinkle, J. Kim, R.M. Wallace
Abstract: Atomic layer deposition (ALD) of high dielectric constant (high-k) materials for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology has now resulted in the investigation of transistors incorporating alternative channel materials, such as III-V compounds. The control of the interfacial chemistry between a high-k dielectric and III-V materials presents a formidable challenge compared to that surmounted by Si-based technologies. The bonding configuration is obviously more complicated for a compound semiconductor, and thus an enhanced propensity to form interfacial defects is anticipated, as well as the need for surface passivation methods to mitigate such defects. In this work, we outline our recent results using in-situ methods to study the ALD high-k/III-V interface. We begin by briefly summarizing our results for III-As compounds, and then further discuss recent work on III-P and III-Sb compounds. While arsenides are under consideration for nMOS devices, antimonides are of interest for pMOS. InP is under consideration for quantum well channel MOS structures in order to serve as a better nMOS channel interface. In all cases, a high-k dielectric interface is employed to limit off-state tunneling current leakage.
Authors: Matthias Müller, Sonja Sioncke, Annelies Delabie, Burkhard Beckhoff
Abstract: Thin films of high-k material are becoming more and more used for semiconductor devices. A further shrinking of the devices requires also a further reduction of the high-k film thickness. With this reduction of the high-k thickness down to just a few nanometers two technical challenges have to be addressed. The first one is the ALD process for the deposition of the high-k material. Usually the ALD process can be well controlled by tuning the number of process cycles. But it is theoretically predicted [1] that the growth-per-cycle of the first cycles can be different than the steady growth-per-cycle which is obtained for high cycle numbers. This effect is caused by a not fully covered initial surface during the first cycles. Only when the deposited material forms a closed surface and the surface probabilities are the same for each following cycle the deposition rate will be constant. The second challenge is that the electrical properties of thin films with a thickness of a few nanometers are significantly determined by the quality of the interface between the film and the substrate.
Authors: George G. Totir, Mahmoud Khojasteh, Ronald Nunes, Emanuel I. Cooper, Matthew Kern, Kim van Berkel, Makonnen Payne, Ronald Dellaguardia, Bang To, Siegfried Maurer
Abstract: An all-wet process based on a novel chemistry has been developed to enable the removal of high-dose implanted photoresist in the presence of exposed metal layers and other materials typical of advanced gate stacks.
Authors: Niladri Pratap Maity, Rajiv R. Thakur, Reshmi Maity, R.K. Thapa, S. Baishya
Abstract: In this paper the interface trap densities (Dit) are analyzed for ultra thin dielectric material based metal oxide semiconductor (MOS) devices using high-k dielectric material Al2O3. The Dit have been calculated by a novel approach using conductance method and it indicates that by reducing the thickness of the oxide, the Dit increases and similar increase is also found by replacing SiO2 with Al2O3. For the same oxide thickness SiO2 has the lowest Dit and found to be the order of 1011 cm-2eV-1. The Dit is found to be in good agreement with published fabrication results at p-type doping level of 1 × 1017 cm-3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.
Authors: Enrico Bellandi, Barbara Crivelli, Mauro Alessandri
Authors: Peter M. Gammon, Amador Pérez-Tomás, Michael R. Jennings, Owen J. Guy, N. Rimmer, J. Llobet, Narcis Mestres, Phillippe Godignon, Marcel Placidi, M. Zabala, James A. Covington, Philip A. Mawby
Abstract: In this paper, the integration of HfO2 onto SiC has been investigated via a number of different test structures. Capacitors consisting of HfO2 on Si, SiC, Si/SiC and SiO2/SiC have been fabricated and electrically tested. The new HfO2/Si/SiC capacitors provide the greatest breakdown electric field of 3.5 MV/cm, whilst leakage currents are minimised through the insertion of the narrow bandgap material. The Si layer, which is wafer bonded to the SiC, is proven to be stress free through Raman spectroscopy, whilst TEM and EDX prove that the interface is free of contaminants.
Authors: J.H. Hong, Jae Min Myoung
Abstract: The chemical and electrical characteristics of HfO2 dielectric layers grown on the p-type Si substrate by the metalorganic molecular beam epitaxy (MOMBE) technique were investigated. The XPS spectra showed that the Hf 4f and O 1s peaks shifted to the higher level of binding energy due to the charge 1transfer effect. Electrical properties were analyzed by C-V and I-V measurements. The distortion of C-V curve at depletion region is attributed to the effect of deep trap levels’ existence. Saturation capacitance and leakage current density were in the range of 207 ~ 249 pF and 0.52 ~ 0.58 A/cm2 respectively, and the flat band voltage shift to the higher voltage appeared as the oxygen flow rate increased.
Authors: Jing Hua Xia, David M. Martin, Sethu Saveda Suvanam, Carl Mikael Zetterling, Mikael Östling
Abstract: LaxHfyO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N2O ambient. The result shows that high quality LaxHfyO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.
Authors: Niladri Pratap Maity, R.K. Thapa, S. Baishya
Abstract: In this paper different characteristic parameters using high-k dielectric materials in Metal Oxide Semiconductor (MOS) device have been compared from the theoretical and simulated Capacitance-Voltage (C-V) graphs. The simulation has been done using ATLAS device simulator. The agreement of the specified values while deriving and simulating and that extracted is excellent. Further, the extracted parameters for high-k dielectric materials show an inferior interfacial quality.
Authors: Pascal Besson, Virginie Loup, Thierry Salvetat, Névine Rochat, Sandrine Lhostis, Sylvie Favier, Karen Dabertrand, Vincent Cosnier
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