Papers by Keyword: High Speed Wafer Rotation Vertical CVD Tool

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Authors: Yoshiaki Daigo, Akio Ishiguro, Shigeaki Ishii, Hideki Ito
Abstract: In this study, influence of both Si/H2 ratio and C/Si ratio on growth rate uniformity and carrier concentration uniformity of n-type 4H-SiC epitaxial films grown by high speed wafer rotation vertical CVD tool was investigated. It was found that changes in radial profile of the growth rate and the carrier concentration obtained by varying Si/H2 ratio showed quite similar behavior to those obtained by varying C/Si ratio. Such a similar trend would suggest that the distribution of local C/Si ratio near the wafer surface changes depending on total Si/H2 ratio similarly to total C/Si ratio. Additionally, by using this relationship, both the growth rate uniformity of 49.2 μm/h ±1.78% (1.15% σ/mean) and carrier concentration uniformity of 1.08 ×1016cm-3 ±6.15% (3.40% σ/mean) was achieved.
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Authors: Yoshiaki Daigo, Akio Ishiguro, Shigeaki Ishii, Hideki Ito
Abstract: 4H-SiC homo-epitaxial films were grown using a high speed wafer rotation vertical CVD tool, and effects of wafer rotation speed during initial temperature ramping before epitaxial growth were investigated. Also, the effects of conditions during growth of the highly doped buffer layer on both surface and PL defect densities were investigated. It was found that the wafer rotation speed during the temperature ramping has a large influence on the surface defect density of the films. Especially, triangles generated from small pits were considerably reduced in the samples grown at a higher wafer rotation speed during the temperature ramping. The phenomena could be explained as a result of suppressed interfacial reaction between down-falls (DFs) and the wafer surface. Additionally, it was found that the density of basal plane dislocations (BPDs) on a drift layer is remarkably reduced by adjusting the C/Si ratio during growth of the buffer layer grown prior to the drift layer. By applying higher wafer rotation speed during the temperature ramping and optimizing the C/Si ratio for the growth of the buffer layer, a total defect density of 0.75 cm-2 on the film, which includes DFs, triangles, DF-triangles, stacking faults (SFs) and BPDs, was achieved.
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