Papers by Keyword: High Temperature Annealing

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Authors: Atsushi Tanaka, Naoyuki Kawabata, Masatoshi Tsujimura, Yukihiro Furukawa, Taizo Hoshino, Yoshinori Ueji, Kazuhiko Omote, Hirotaka Yamaguchi, Hirofumi Matsuhata, Kenji Fukuda
Abstract: In this study, we investigated the annealing temperature dependence of dislocation extension in an ion-implanted region of a 4H-silicon carbide (SiC) C-face epitaxial layer, revealing that a high temperature annealing led to dislocation formation. We also investigated the current-voltage (I-V) characteristics of a 4H-SiC PIN diode with and without these extended dislocations. We demonstrated that the forward biased I-V characteristics of samples with extended interfacial dislocations have a kink at lower current regions.
Authors: Kazuki Tajima, Woosuck Shin, Maiko Nishibori, Norimitsu Murayama, Toshio Itoh, Noriya Izu, Ichiro Matsubara
Abstract: Micro-thermoelectric hydrogen sensor (micro-THS) with the combination of the thermoelectric effect of Si0.8Ge0.2 thin film and the Pt-catalyzed exothermic reaction of hydrogen oxidation was prepared by microfabrication process. In the viewpoint of high sensitivity of micro-THS, the thermoelectric properties of the Si0.8Ge0.2 thin film could be improved by optimizing carrier concentration using helicon sputtering with an advantage of easy doping control, and sensitivity of the device with this thin film was investigated. As the result, the boron-doped Si0.8Ge0.2 thin film is considered to be the better choice ensuring the reliable monitoring of hydrogen concentration down to ppm level.
Authors: Hideaki Tanaka, Satoshi Tanimoto, Mitsugu Yamanaka, Masakatsu Hoshi
Authors: Serguei I. Maximenko, Jaime A. Freitas, N.Y. Garces, E.R. Glaser, Mark A. Fanton
Abstract: The behavior of the D1 center in semi-insulating 4H-SiC substrates revealed by low-temperature photoluminescence was investigated after post-growth high temperature anneals between 1400 and 2400oC. The influence of different post-anneal cooling rates was also studied. The optical signature of D1 was observed up to 2400oC with intensity maxima at 1700 and 2200oC. We propose that the peak at 1700°C can be related to the formation and subsequent dissociation of SiC native defects. It was found that changes in the post-annealing cooling rate drastically influence the behavior of the D1 center and the concentrations of the VC, VSi, VC-VSi and VC-CSi lattice defects.
Authors: Julien Nicolai, Nelly Burle, Bernard Pichaud
Abstract: High temperature annealing effects on Oxygen-induced defects formation has been studied by IR-LST, FTIR and TEM techniques. The results show that most defects are amorphous oxygen precipitates and/or dislocations. Ham’s theory has been modified in order to take into account the variations of interstitial oxygen concentration during the formation of precipitates. Comparison between experimental data and simulation shows that the specificity of annealing cycle is to combine both nucleation and growth stages. The morphology and stoechiometry of SiOx precipitates are also studied.
Authors: N. Tsuchiya, Hideyoshi Matsushita, J. Sugamoto, Akira Kawasaki, Hiroshi Kubota
Authors: S. Nadahara, H. Kubota, S. Samata
Authors: Akimasa Kinoshita, Takashi Nishi, Tsutomu Yatsuo, Kenji Fukuda
Abstract: Ion implantation and a subsequent annealing at high temperature are required for fabricating a high voltage Schottky Barrier Diode (SBD) with a field limiting ring (FLR) or a junction termination extension (JTE), but high temperature annealing degrades surface condition of a SiC substrate and induces a degradation of electronic characteristics of a fabricated SBD. To avoid a degradation of SBD electronic characteristics after high temperature annealing, the method of removing a degraded layer from a SiC surface by sacrificial oxidation after high temperature annealing is studied. In this study, we studied the relationship between the improvement of SBD electronic characteristics and the thickness of sacrificial oxide grown after high temperature annealing. 9~12 SBD without edge termination were fabricated on a SiC substrate of 4mm×4mm. The ratio of good chips to all chips (9~12 SBD) increases with increasing total thickness of sacrificial oxide grown after high temperature annealing at 1800oC for 30 s, where an SBD with a leakage current less than 1μA/cm2 at reverse voltage of –100V was defined as a good chip. We applied this process growing sacrificial oxide of 150nm after high temperature annealing to fabricate the SBD with an FLR structure designed with 600V blocking voltage on a Si-face SiC substrate. The SBD with an FLR structure through this process of 150 nm sacrificial oxide is low leakage current of less than 1μA/cm2 at reverse voltage of –100V and achieves 600V blocking voltage, however, the SBD with an FLR structure without the process of sacrificial oxide after high temperature annealing is high leakage current at reverse voltage of –100V. It is shown that this process growing sacrificial oxide after high temperature annealing is useful to fabricate an SBD with an FLR structure.
Authors: H. Schmitt, Volker Haeublein, Anton J. Bauer, Lothar Frey
Abstract: The impact of implantation temperature and dose as well as the annealing process with and without a graphite capping layer on surface roughness, carrier mobility and specific contact resistance are investigated and compared. The use of the capping layer is proven to be particularly advantageous: (1) a deterioration of surface roughness can be avoided even for high dose implantations and (2) the specific contact resistance is reduced. Furthermore, it is shown that a capping layer prevents surface contamination during annealing.
Authors: Andreas Gällström, Björn Magnusson, Patrick Carlsson, Nguyen Tien Son, Anne Henry, Franziska Christine Beyer, Mikael Syväjärvi, Rositza Yakimova, Erik Janzén
Abstract: The influence of different cooling rates on deep levels in 4H-SiC after high temperature annealing has been investigated. The samples were heated from room temperature to 2300°C, followed by a 20 minutes anneal at this temperature. Different subsequent cooling sequences down to 1100°C were used. The samples have been investigated using photoluminescence (PL) and IV characteristics. The PL intensities of the silicon vacancy (VSi) and UD-2, were found to increase with a faster cooling rate.
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