Papers by Keyword: Hole Traps

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Authors: Patrick Fiorenza, Filippo Giannazzo, Alessia Frazzetto, Alfio Guarnera, Mario Saggio, Fabrizio Roccaforte
Abstract: This paper reports on the conduction mechanisms through the gate oxide and trapping effects at SiO2/4H-SiC interfaces in MOS-based devices subjected to post deposition annealing in N2O. The phenomena were studied by temperature dependent current–voltage measurements. The analysis of both n and p-MOS capacitors and of n-channel MOSFETs operating in the “gate-controlled-diode” configuration revealed an anomalous hole conduction behaviour through the SiO2/4H-SiC interface, with the onset of current conduction moving towards more negative values during subsequent voltage sweeps. The observed gate current instabilities upon subsequent voltage sweeps were deeply investigated by temperature dependent cyclic gate current measurements. The results were explained by the charge-discharge mechanism of hole traps in the oxide.
705
Authors: Yan Jing He, Hong Liang Lv, Xiao Yan Tang, Qing Wen Song, Yi Meng Zhang, Yu Ming Zhang
Abstract: P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.
667
Authors: Yoshihito Katsu, Takuji Hosoi, Yuichiro Nanen, Tsunenobu Kimoto, Takayoshi Shimura, Heiji Watanabe
Abstract: We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.
599
Authors: S. Scharf, M. Schmidt, D. Bräunig
91
Authors: L. Storasta, F.H.C. Carlsson, S.G. Sridhara, Boleslaw Formanek, Peder Bergman, Anders Hallén, Erik Janzén
431
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