Papers by Keyword: III-V Semiconductor

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Authors: D.J. Chadi, C.H. Park
Authors: Mi Jung, Seok Lee, Young Tae Byun, Young Min Jhon, Sun Ho Kim, Sun Il Mho, Deok Ha Woo
Abstract: Formation of size controlled nanohole arrays on semiconductor substrate can be used variously in applications of photonic and electronic device. The unique structure of nanoporous alumina was directly used as an etching mask for pattern transfer into the GaAs substrate. Using the alumina masks prepared at the anodic voltage of 24 V in 0.3 M sulfuric acid solution and 40 V in 0.3 M oxalic acid solution, fabricated were the arrays of nanohole on GaAs substrate by inductively coupled plasma reactive ion etching (ICP-RIE). The etching was conducted in a SiCl4/Ar mixed gas system. The uniform nanohole arrays were formed as replica of ordered lattice pattern of the mask. Depending on property of the alumina mask used, the size of nanohole was controlled to have hole diameter of 60 nm (with the hole density of 1.0 x 1010 cm-2) and of 30 nm (with the hole density of 2.7 x 1010 cm-2), respectively. So, the alumina mask attached on the GaAs substrate mainly determines the distribution and the size of the nanohole arrays. ICP-RIE using nanoporous alumina masks can control the size and the density of nanohole on compound semiconductor substrate.
Authors: A. Geizutis, A. Krotkus, A. Reklaitis, M. Asche
Authors: Goutam Kumar Dalapati, Avishek Kumar, Andrew See Weng Wong, Manippady Krishna Kumar, Ching Kean Chia, Ghim Wei Ho, Dong Zhi Chi
Abstract: Sputtered-deposited ZrO2 gate dielectric on epitaxial-GaAs/Ge substrates have been studied for complementary-metal-oxide-semiconductor (CMOS) applications. The epitaxial-GaAs (epi-GaAs) on Ge susbstrates with AlGaAs interlayer was grown by metal-organic chemical vapor deposition at 650oC. High resolution transmission electron microscopy ((HRTEM) shows that the epilayers are free from arsenic anti-phase defects (APD). From secondary ion mass spectrometry, it was confirmed that the Ge diffusion is completely blocked by the AlGaAs layer and no Ge atoms are able to penetrate into the GaAs layer. The macroscopic surface roughness of epitaxial GaAs is ~5.3nm, whereas over 200x200nm is 0.4 nm, which is comparable with bulk GaAs. Althogh, the epi-GaAs has nano-scale surface features; the conduction-AFM shows electrically homogeneous surface. The electrical and interfacial properties of MOS capacitors with sputtered deposited ZrO2 dielectric on epitaxial-GaAs/Ge and bulk GaAs substrates were investigated. The frequency dispersion and hysteresis voltage for directly deposited ZrO2 on epi-GaAs is higher compared with bulk p-GaAs, however, it is comparable with bulk n-GaAs. The interfacial and electrical properties of ZrO2 on epi-GaAs have shown to exhibit better electrical characteristics after post deposition annealing (PDA) at 400oC. The apparent doping profile of the epitaxial layer is unchanged with PDA temperatures, which suggest the less cross-diffusion of Ge, Ga, and As during device fabrication. The degradation of the gate oxide quality and interface properties are mainly due to the high surface roughness of epitaxial layer and also presence of elemental out diffusion of Ga and As.
Authors: Sang Woo Lim
Abstract: The integration of III-V and Ge materials on Si surface causes many issues with complexity such as lattice mismatch with silicon. In particular, the surface preparation and passivation of InGaAs is very challenging, because the formation of InGaAs/high-K interface is important, but not well understood. For the systematical study of InGaAs surface during wet processes, the effect of various wet etching processes on the surfaces of binary III-V compound semiconductors (GaAs, InAs, GaSb and InSb) was studied from the viewpoints of surface oxidation, material loss (dissolution), and passivation. Based on that, further effort to understand the surface reactions on ternary InGaAs compound semiconductor was made. In addition, process sequential effect on the InGaAs surface was investigated.
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