Papers by Keyword: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

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Authors: Eiichi Okuno, Takeshi Endo, Jun Kawai, Toshio Sakakibara, Shoichi Onda
Abstract: We have investigated the techniques to improve the channel mobility of SiC MOSFETs and found that the hydrogen termination of dangling bonds at a MOS interface is very effective in improving the channel mobility, particularly that of the interface fabricated on a (11-20) face wafer. A high channel mobility of MOSFET on the (11-20) face was achieved to 244cm2/Vs by new process which can terminate dangling bonds by hydrogen. The vertical MOSFET, which is prepared using this process, has a low on-resistance of 5.7 mΩcm2 and a breakdown voltage of 1100 V. The channel resistance is estimated at 0.58 mΩcm2.
Authors: Kuniaki Yagi, Takamitsu Kawahara, Naoki Hatta, Hiroyuki Nagasawa
Abstract: A new technique that reduces stacking fault (SF) density in 3C-SiC, termed switch-back epitaxy (SBE), is demonstrated regarding its effects on morphological and electrical properties. SBE is a homoepitaxial growth process on backside of 3C-SiC grown on undulant-Si. The key feature of SBE, the surface polarity of residual SFs in 3C-SiC, which cannot be erased by heteroepitaxial growth on undulant-Si, is converted from the Si-face to the C-face. The SF density on the surface of 3C-SiC grown by SBE shows a remarkable decrease to one-seventh lower than that on undulant- Si. The leakage current of pn-diode epitaxially fabricated on the 3C-SiC substrate grown by SBE decreases to as low as one-thirtieth that on 3C-SiC substrate grown without SBE. These results suggest that SBE eliminates the SFs on the surface of 3C-SiC and subsequently reduces the leakage current at pn-junction thus fabricated.
Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.
Authors: Anant K. Agarwal, Jeff B. Casady, L.B. Rowland, W.F. Valek, C.D. Brandt
Authors: Shinsuke Harada, Makoto Kato, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Kazuo Arai
Abstract: The channel mobility in the SiC MOSFET degrades on the rough surface of the p-well formed by ion implantation. Recently, we have developed a double-epitaxial MOSFET (DEMOSFET), in which the p-well comprises two stacked epitaxially grown p-type layers and an n-type region between the p-wells is formed by ion implantation. This device exhibited a low on-resistance of 8.5 mcm2 with a blocking voltage of 600 V. In this study, to further improve the performance, we newly developed a device structure named implantation and epitaxial MOSFET (IEMOSFET). In this device, the p-well is formed by selective high-concentration p+ implantation followed by low-concentration p- epitaxial growth. The fabricated IEMOSFET with a buried channel exhibited superior characteristics to the DEMOSFET. The extremely low specific on-resistance of 4.3 mcm2 was achieved with a blocking voltage of 1100 V. This value is the lowest in the normally-off SiC MOSFETs.
Authors: Jim Richmond, Sei Hyung Ryu, Sumi Krishnaswami, Anant K. Agarwal, John W. Palmour, Bruce Geil, Dimos Katsis, Charles Scozzie
Abstract: This paper reports on a 400 watt boost converter using a SiC BJT and a SiC MOSFET as the switch and a 6 Amp and a 50 Amp SiC Schottky diode as the output rectifier. The converter was operated at 100 kHz with an input voltage of 200 volts DC and an output voltage of 400 volts DC. The efficiency was tested with an output loaded from 50 watts to 400 watts at baseplate temperatures of 25°C, 100°C, 150°C and 200°C. The results show the converter in all cases capable of operating at temperatures beyond the range possible with silicon power devices. While the converter efficiency was excellent in all cases, the SiC MOSFET and 6 Amp Schottky diode had the highest efficiency. Since the losses in a boost converter are dominated by the switching losses and the switching losses of the SiC devices are unaffected by temperature, the efficiency of the converter was effectively unchanged as a function of temperature.
Authors: Qamar-ul Wahab, Hajime Kosugi, Hiroshi Yano, Christer Hallin, Tsunenobu Kimoto, Hiroyuki Matsunami
Authors: Toshiya Yokogawa, Kunimasa Takahashi, Osamu Kusumoto, Masao Uchida, Kenya Yamashita, Makoto Kitabatake
Authors: Seiji Suzuki, Shinsuke Harada, Tsutomu Yatsuo, Ryouji Kosugi, Junji Senzaki, Kenji Fukuda
Authors: Mitsuo Okamoto, Seiji Suzuki, Makoto Kato, Tsutomu Yatsuo, Kenji Fukuda
Abstract: We have fabricated lateral RESURF MOSFETs on 4H-SiC(0001) Si-face and (000-1) C-face substrates, and compared those properties. The channel mobility of a lateral test MOSFET on a C-face was 41 cm2/Vs, which was much higher than 5 cm2/Vs for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was improved to 79 mΩcm2 as comparison with 2400 mΩcm2 for Si-face. The breakdown voltage was 490V for Si-face and 460V for C-face, which was 82% and 79% of the designed breakdown voltage of 600V, respectively. The device breakdown occurred destructively at the gate electrode edge.
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