Papers by Keyword: Minority Carrier Lifetime

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Authors: L. Masarotto, Jean Marie Bluet, I. El Harrouni, Gérard Guillot
Authors: Xian Pei Ren, Peng Wu, Shuai Li, Hao Ran Cheng, Wen Xiu Gao, Chao Chen
Abstract: In this paper, we investigated the characterization of a gallium co-doping multicrystalline silicon ingot made of solar-grade silicon purified by metallurgical route. It is shown that the addition of gallium yields a fully p-type ingot and resistivity distribution in the range from 1.2 Ω.cm to1.7 Ω.cm along the full ingot height. Minority carrier lifetime measurements indicate that this material is suitable for the production of solar cells with comparable efficiencies to standard material. In addition, gallium addition in compensated silicon during ingot casting is proved to be very prospective for controlling the resistivity and increasing material yield of ingot.
Authors: K.Y. Cheong, Sima Dimitrijev, Ji Sheng Han
Authors: Filippo Nava, P. Vanni, G. Verzellesi, Antonio Castaldini, Anna Cavallini, L. Polenta, Roberta Nipoti, C. Donolato
Authors: Maral Azizi, Elke Meissner, Jochen Friedrich
Abstract: In this work laboratory scale multicrystalline silicon ingots were grown which have been intentionally contaminated with iron in the range between 10 to 400 ppmw by adding FeSi2 to the silicon feedstock. It is shown that an iron contamination at these high levels does not result in a structural breakdown of the columnar grain growth regime because constitutional supercooling could be avoided by strong mixing of the melt in the present crystal growth experiments. The minority carrier lifetime mappings are dominated by the iron contamination and show the distribution of the impurity over the ingot height. The measured values of the specific electrical resistivity show a significant drop from 40 to below 20 Ωcm for a contamination level of 10 ppmw Fe probably due to interactions of iron with thermal donors. At higher contamination levels the specific resistivity increases significantly with increasing iron concentration compared to the 10 ppmw ingot. Above 400 ppmw iron the specific resistivity drops below the initial value for nominally iron free material. These results indicate that interstitial iron shows a donor-like behavior in multicrystalline silicon and precipitated iron decreases the specific resistivity.
Authors: Sung Wook Huh, Joseph J. Sumakeris, A.Y. Polyakov, Marek Skowronski, Paul B. Klein, B.V. Shanabrook, Michael J. O'Loughlin
Abstract: Carrier lifetimes and the dominant electron and hole traps were investigated in a set of thick (9-104mm) undoped 4H-SiC epitaxial layers grown by CVD homoepitaxy. Deep trap spectra were measured by deep level transient spectroscopy (DLTS) with electrical or optical injection, while lifetimes were measured by room temperature time-resolved photoluminescence (PL). The main electron traps detected in all samples were due to Ti, Z1/Z2 centers, and EH6/EH7 centers. Two boron-related hole traps were observed with activation energies of 0.3 eV (boron acceptors) and 0.6 eV (boron-related D centers). The concentration of electron traps decreased with increasing layer thickness and increased toward the edge of the wafers. PL lifetimes were in the 400 ns-1800 ns range with varying injection and generally correlated with changes in the density of Z1/Z2 and to a lesser extent the EH6/EH7 electron traps. However, the results of DLTS measurements on p-i-n diode structures suggest that the capture of injected holes is much more efficient for the Z1/Z2 traps compared to the EH6/EH7 centers making the Z1/Z2 more probable candidates for the role of lifetime killers. A good fit of the thickness dependence of the measured lifetimes to the usual analytical form was obtained assuming that Z1/Z2 is the dominant hole recombination center and that the surface recombination velocity was 2500 cm/sec.
Authors: Koichiro Saga
Abstract: Metallic contamination on silicon surfaces has a detrimental impact on ULSI device performance and yield. Surface metal impurities degrade gate oxide integrity while metal impurities dissolved in silicon cause recombination centers and result in junction leakage. Surface metal impurities penetrate silicon by the colliding with dopant during ion implantation and are also diffused in silicon by subsequent annealing [. The diffusion behavior of metal impurities in silicon is well-known [. While metal impurities often penetrate silicon through the silicon oxide in ULSI processing, little work has been reported on the diffusion behavior of metal impurities penetrating silicon oxide. We demonstrated the diffusion behavior of metal impurities penetrating silicon substrates with different thickness of silicon oxide by the collision with dopant during ion implantation.
Authors: Qiu Yan Hao, Xin Jian Xie, Bing Zhang Wang, Cai Chi Liu
Abstract: In order to investigate the performance of silicon single crystal depended on the annealing temperature, the minority carrier lifetime, the resistivity and oxygen concentration after different temperature annealing in Ar ambient were examined. And the effect of oxygen and related defects formed during annealed on the minority carrier lifetime were analyzed by microwave photoconductivity method, Fourier transform infrared spectrometer and four-probe measurement. The results indicate that after 450°C annealing for 30h, the resistivity and minority carrier lifetime of silicon increase significantly, while the concentration of interstitial oxygen decreases. After the annealing at 650°C, oxygen donor can be removed and the resistivity and the minority carrier lifetime decrease. During the high-temperature (above 650°C) annealing, the oxygen precipitation can decrease the minority carrier lifetime silicon.
Authors: Jia Yan Li, Yi Tan, Mei Liu, Wei Dong
Abstract: The Si3N4 protective coating has an important impact on avoiding melting silicon from contacting with the crucible wall directly. A mixed Si/Si3N4 layer was formed on the interface of silicon and Si3N4 coating, and the declination of N content was observed in this mixed layer. With the ingots condition of 1500oC for 2 h, the large Si3N4 and SiC particles appeared in the mixed layer and the formation mechanism was discussed. The Si3N4 coating had significantly increased the lifetime of minority carriers by decreasing impurity content.
Authors: Jiao Li, Xiu Hua Chen, Wen Hui Ma, Cong Zhang, Kui Xian Wei
Abstract: The multicrystalline silicon wafers purified by directional solidification route were used to introduce copper impurities. The resistivity and minority carrier lifetime of multicrystalline silicon wafers were investigated by four-point probe resistivity tester and μ-PCD, respectively. Annealing temperature, atmosphere and cooling rate were researched. It was found that copper contaminants have a greater impact on the electrical properties of multicrystalline silicon. Research results showed that copper impurities tend to exist at defect sites at high temperature, and high annealing temperature, argon atmosphere and slow cooling conditions make more impact on the electrical properties of multicrystalline silicon than low annealing temperature, air atmosphere and fast cooling.
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