Papers by Keyword: MOS Capacitor

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Authors: Svetlana Beljakowa, Thomas Frank, Gerhard Pensl, Kun Yuan Gao, Florian Speck, Thomas Seyller
Abstract: An alternative oxidation technique is developed and built up, which provides monatomic oxygen during the whole oxidation process. The set-up consists of a tungsten lamp furnace and a microwave-plasma. A number of different gases can be introduced into the oxidation quartz tube. In addition, an Al2O3-layer is deposited on a part of the oxide layers by atomic layer chemical vapor deposition (ALCVD). First oxidation runs result in encouraging low values of the density of interface states Dit and in the flatband voltage UFB. It turns out that with the present experimental conditions, the comparison of MOS capacitors fabricated with different dielectric layers favors gate dielectrics grown in O2/N2-ambient.
Authors: Harsh Naik, T. Paul Chow
Abstract: This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400°C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.
Authors: Amador Pérez-Tomás, Dominique Tournier, Phillippe Godignon, Narcis Mestres, José Millan
Abstract: Thin (~10nm) Si layers have been deposited using Rapid Thermal CVD at temperatures ranging 950°C-1050°C. RTCVD deposited Si layers have been oxidized using N2O at 1300°C during relatively short times (15min) to produce SiO2 layers of 20-30nm. The interfacial characteristics of N2O oxidized RTCVD layers have been studied using the conductance method, showing a reduced traps density and a low band bending fluctuation when compared with conventional N2O grown oxides on 4H-SiC substrates. The surface topology of these layers has also been analyzed evidencing an adequate topography with low roughness.
Authors: Frédéric Lanois, Dominique Planson, P. Lassagne, Christophe Raynaud, Edwige Bano
Authors: Kenji Fukuda, Junji Senzaki, Mitsuhiro Kushibe, Kazutoshi Kojima, Ryouji Kosugi, Seiji Suzuki, Shinsuke Harada, Takaya Suzuki, Tomoyuki Tanaka, Kazuo Arai
Authors: Hironori Yoshioka, Takashi Nakamura, Junji Senzaki, Atsushi Shimozato, Yasunori Tanaka, Hajime Okumura, Tsunenobu Kimoto
Abstract: We focused on the inability of the common high-low method to detect very fast interface states, and developed methods to evaluate such states (CψS method). We have investigated correlation between the interface state density (DIT) evaluated by the CψS method and MOSFET performance, and found that the DIT(CψS) was well reflected in MOSFET performance. Very fast interface states which are generated by nitridation restricted the improvement of subthreshold slope and field-effect mobility.
Authors: Le Shan Chan, Yu Hao Chang, Kung Yen Lee
Abstract: ZrO2 films were deposited on C-face 4H-SiC substrates by using an RF sputter at a temperature of 200°C. Then, ZrO2 films were treated with RTA (rapid thermal annealing) process in Argon (Ar) ambient at 600°C, 700°C and 800°C for 4 minutes, respectively. The samples with RTA process show the lower leakage currents. As the measure temperature increases from room temperature (RT) to 150°C, the dielectric breakdown voltage reduces from 3 V to 1 V. The difference between quasi C-V characteristics and high frequency C-V characteristics at 1 MHz becomes larger with increasing RTA temperature. The C-V curves also shift to the left side as the measure temperature increases from RT to 150°C. It also shows the ledge on the C-V curves of samples with RTA at elevated measure temperature.
Authors: Sandip Kumar Roy, Jesus Urresti Ibanez, Anthony G. O’Neill, Nick G. Wright, Alton B. Horsfall
Abstract: Oxygen free Ohmic contacts are essential for the realisation of high performance devices. Ohmic contacts in SiC often require annealing under vacuum at over 1000 °C, whilst high-κ dielectrics are usually annealed in O2 rich ambient at temperatures of 800 °C or less, affecting the electrical and surface characteristics. Therefore, protection of the Ohmic contacts during the annealing of a high-κ dielectric layer is a key enabling step in the realisation of high performance MOS structures. In order to prevent damage during the high-k formation the use of silicon nitride as a passivation layer, capable of protecting the contacts during annealing, has been investigated. In this work we have investigated and compared silicon nitride protected high-κ dielectric SiC based MOS capacitors with the unprotected SiC MOS devices in terms of electrical and optical characteristics.
Authors: Peter M. Gammon, Amador Pérez-Tomás, Michael R. Jennings, Owen J. Guy, N. Rimmer, J. Llobet, Narcis Mestres, Phillippe Godignon, Marcel Placidi, M. Zabala, James A. Covington, Philip A. Mawby
Abstract: In this paper, the integration of HfO2 onto SiC has been investigated via a number of different test structures. Capacitors consisting of HfO2 on Si, SiC, Si/SiC and SiO2/SiC have been fabricated and electrically tested. The new HfO2/Si/SiC capacitors provide the greatest breakdown electric field of 3.5 MV/cm, whilst leakage currents are minimised through the insertion of the narrow bandgap material. The Si layer, which is wafer bonded to the SiC, is proven to be stress free through Raman spectroscopy, whilst TEM and EDX prove that the interface is free of contaminants.
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