Papers by Keyword: On-Resistance

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Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.
Authors: Q. Jon Zhang, Charlotte Jonas, Joseph J. Sumakeris, Anant K. Agarwal, John W. Palmour
Abstract: DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).
Authors: Siddarth G. Sundaresan, Charles Sturdevant, Madhuri Marripelly, Eric Lieser, Ranbir Singh
Abstract: Sharp avalanche breakdown voltages of 12.9 kV are measured on PiN rectifiers fabricated on 100 µm thick, 3 x 1014 cm-3 doped n- epilayers grown on n+ 4H-SiC substrates. This equates to a record high 129 V/µm for a > 10 kV device. Optimized epilayer, device design and processing of the SiC PiN rectifiers result in a > 60% blocking yield at 10 kV, ultra-low on-state voltage drop and differential on-resistance of 3.75 V and 3.3 mΩ-cm2 at 100 A/cm2 respectively. Open circuit voltage decay (OCVD) measured carrier lifetimes in the range of 2-4 µs are obtained at room temperature, which increase to a record high 14 µs at 225 °C. Excellent stability of the forward bias characteristics within 10 mV is observed for a long-term forward biasing of the PiN rectifiers at 100 A/cm2. A PiN rectifier module consisting of five parallel large area 6.4 mm x 6.4 mm 10 kV PiN rectifiers is connected as a free-wheeling diode with a Si IGBT and 1100 V/100 A switching transients are recorded. Data on the current sharing capability of the PiN rectifiers is also presented.
Authors: Shinsuke Harada, Yusuke Kobayashi, A. Kinoshita, N. Ohse, Takahito Kojima, M. Iwaya, Hiromu Shiomi, Hidenori Kitai, Shinya Kyogoku, Keiko Ariyoshi, Yasuhiko Onishi, Hiroshi Kimura
Abstract: A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.
Authors: Yasunori Tanaka, Koji Yano, Mitsuo Okamoto, Akio Takatsuka, Kazuo Arai, Tsutomu Yatsuo
Abstract: We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.
Authors: Takashi Tsuji, Hiromu Shiomi, Naoyuki Ohse, Yasuhiko Onishi, Kenji Fukuda
Abstract: In this paper, newly developed 3300V-class IEMOSFETs were presented. By means of the optimization of current spreading layers (CSLs), we could achieve low specific on-resistance (RONA) of 11.6mΩcm2, while maintaining high blocking voltage (BVDSS) of 3978V. The RONA analysis revealed drastic reduction of JFET resistance compared to a MOSFET without a CSL. High ruggedness with the avalanche withstanding energy of 4.6J/cm2 was achieved by the optimal device design of the edge termination. We could also confirm favorable characteristics of RONA, BVDSS and threshold voltage (VTH) at high temperatures up to 200C, and the fast switching behavior.
Authors: Motoki Kobayashi, Hidetsugu Uchida, Akiyuki Minami, Toyokazu Sakata, Romain Esteve, Adolf Schöner
Abstract: 3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.
Authors: Shinsuke Harada, Makoto Kato, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Kazuo Arai
Abstract: The channel mobility in the SiC MOSFET degrades on the rough surface of the p-well formed by ion implantation. Recently, we have developed a double-epitaxial MOSFET (DEMOSFET), in which the p-well comprises two stacked epitaxially grown p-type layers and an n-type region between the p-wells is formed by ion implantation. This device exhibited a low on-resistance of 8.5 mcm2 with a blocking voltage of 600 V. In this study, to further improve the performance, we newly developed a device structure named implantation and epitaxial MOSFET (IEMOSFET). In this device, the p-well is formed by selective high-concentration p+ implantation followed by low-concentration p- epitaxial growth. The fabricated IEMOSFET with a buried channel exhibited superior characteristics to the DEMOSFET. The extremely low specific on-resistance of 4.3 mcm2 was achieved with a blocking voltage of 1100 V. This value is the lowest in the normally-off SiC MOSFETs.
Authors: Siddarth Sundaresan, Stoyan Jeliazkov, Ranbir Singh
Abstract: Large-area, 7.84 mm2 SiC DMOSFETs feature breakdown voltages of 4600 V, specific on-resistance of 17 mΩ-cm2 and gate threshold voltage of 2.4 V. The low on-resistance was enabled by an optimized MOS process that resulted in channel mobility as high as 27 cm2/Vs, and oxide breakdown fields in the 10-11 MV/cm range. The key device design and layout parameters were varied to examine the performance versus reliability trade-offs.
Authors: Q. Jon Zhang, Charlotte Jonas, Albert A. Burk, Craig Capell, Jonathan Young, Robert Callanan, Anant K. Agarwal, John W. Palmour, Bruce Geil, Charles Scozzie
Abstract: 4H-SiC BJTs with a common emitter current gain (b) of 108 at 25°C have been demonstrated. The high current gain was accomplished by using a base as thin as 0.25 μm. The current gain decreases at high temperatures but is still greater than 40 at 300°C. The device demonstrates an open emitter breakdown voltage (BVCBO) of 1150 V, and an open base breakdown voltage (BVCEO) of 250 V. A low specific on-resistance of 3.6 mW-cm2 at 25°C was achieved. The BJTs have shown blocking capabilities over a wide range of operating temperatures up to 300°C.
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