Papers by Keyword: Oxide Trap

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Authors: Ronald Green, A.J. Lelis, M. El, Daniel B. Habersat
Abstract: Although high-temperature measurements show a dramatic reduction in the bias-temperature stress-induced threshold-voltage instability of present state-of-the-art devices, a more thorough test methodology shows that several different conclusions may actually be drawn. The particular conclusion depends on the specific post-BTS measurement technique employed. Immediate room-temperature measurements suggest that significant oxide-trap activation may still be occurring. A significant, yet rapid, post-BTS recovery is observed as well. These results underline the importance of making both high-temperature and room-temperature measurements, as a function of stress and recovery time, to better ensure that the full effect of the BTS is observed. Initial AC BTS results suggest a similar level of device degradation as occurs from a DC BTS.
Authors: Daniel B. Habersat, Aivars J. Lelis, Ronald Green, Mooro El
Abstract: Since power devices such as DMOSFETs will operate at higher temperatures with accelerated degradation mechanisms, it is essential to understand the effects of typical operating conditions for power electronics applications. We have found that SiC MOSFETs when gate-biased at 150 °C show an increasing charge pumping current over time, suggesting that interface traps (or perhaps near-interface oxide traps) are being created under these conditions. This trapping increase occurs slightly above linear-with-log-time and mimics previously observed threshold voltage instabilities, though a causal relationship has not yet been determined. We found the charge trapping after 104 s of BTS increased at a rate of 1x1011 cm-2/dec for NBTS (-3 MV/cm), 0.7x1011 cm-2/dec for PBTS (3 MV/cm), and 0.3x1011 cm-2/dec when grounded. The observed increase in charge trapping has negative implications for the long term stability and reliability of SiC MOS devices under operating conditions.
Authors: Aivars J. Lelis, Ronald Green, Daniel B. Habersat
Abstract: We have observed a significant increase in the instability of SiC power MOSFET ID-VGS characteristics following bias stressing at elevated temperature, similar to the effect we previously observed following an ON-state current stress. Devices stressed by elevated temperature alone exhibited very little instability compared with devices stressed with both temperature and applied bias. These results, along with other results in the literature, suggest that this increase in threshold voltage instability at elevated temperature is due to the activation of additional near-interfacial oxide traps related to an O-vacancy defect known as an E′ center. It is important to develop improved processing methods to decrease the number of precursor oxide defect sites, since an increased negative shift can give rise to increased leakage current in the OFF-state and potential device failure if proper precautions are not met to provide an adequate margin for the threshold voltage.
Authors: Daniel B. Habersat, Aivars J. Lelis, Siddharth Potbhare, Neil Goldsman
Abstract: In order to improve Silicon Carbide MOSFET device performance, it is important to minimize the on-state losses by improving the effective channel mobility, which can be done by decreasing interfacial charge consisting of interface traps, fixed charge, and oxide traps, which degrade mobility due to Coulombic scattering. This paper considers a method for distinguishing between oxide traps and fixed charge, and discusses how this charge has varied with processing over the last several years. Our results show that, over the period of study, NF has trended downward. Also, the number of switching oxide traps, which gives a lower bound for Not, appears to have decreased considerably. The trends for improvement in NF and ΔNot are promising, but our data suggests that NF and Not remain much too high and need to be reduced further to realize significant gains in SiC MOSFET performance.
Authors: Vinayak Tilak, Kevin Matocha, Greg Dunne
Abstract: Silicon Carbide (SiC) based metal oxide semiconductor field effect transistors (MOSFETs) were fabricated and characterized using gated hall measurements with different p-type substrate doping concentration (7.2X1016cm-3 and 2X1017 cm-3). An interface trap state density of 5X1013 cm-2eV-1 was observed nearly 0.1 eV above the conduction band edge leading to the conclusion that these states are present in the silicon dioxide rather than the interface. The Hall mobility of the MOSFETs decreased from 26.5 to 20 cm2/Vs as the doping was increased from 7.2X1016 to 2X1017cm-3. The decrease in mobility is primarily due to an increase in the surface electric field that causes an increase in surface roughness scattering. The inversion layer mobility when plotted as a function of average surface electric field is not independent of doping concentration as is the case in silicon MOSFETs because the dominant scattering mechanism is not phonon scattering.
Authors: Daniel B. Habersat, Aivars J. Lelis, J.M. McGarrity, F. Barry McLean, Siddharth Potbhare
Abstract: We have analyzed the effect of post-oxidation nitride anneals (usually with either NO or N2O gases) on SiC MOSFETs. Two 4H:SiC wafers were identically prepared except that one wafer had a nitridation anneal after the gate oxide was formed, while the other was tested as-oxidized. We compared the two processes by making measurements on lateral MOSFETs and MOS capacitors using ID-VGS, C-V, and charge pumping. There was no change in either flatband voltage or interface trap density near the valence band, suggesting that the net fixed charge remained constant (within a few 1011cm-2). However, there was a large shift in the threshold voltage which, when combined with the C-V results, indicates a strong reduction of interface traps near the conduction band of roughly 6.0x1012cm-2 by using the nitridation process. The charge pumping measurements also showed a strong reduction of interface traps. Charge pumping measured a trapping density of 2.5x1012cm-2 for the as-oxidized samples and 5.3x1011cm-2 for the nitrided samples. The frequency-dependence of the charge pumping signal also indicates a spatial distribution of traps, with volumetric trap densities of roughly 1.3x1019cm-3 over 25Å on as-oxidized and 3.8x1018cm-3 over 19Å for nitrided.
Authors: Aivars J. Lelis, Daniel B. Habersat, Ronald Green, Neil Goldsman
Abstract: A two-way tunneling model describing simultaneous oxide trap charging and discharging in SiC MOSFETs is presented, along with a comparison with experimental results. This model can successfully account for the variation in threshold-voltage instability observed as a function of bias-stress time, bias-stress magnitude, and measurement time.
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