Papers by Keyword: Planarization

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Authors: Shi Wen Du, Yong Tang Li, Jian Jun Song, Hui Ping Qi
Abstract: The model proposed integrates process parameters including pressure and velocity and other important input parameters including the wafer hardness, pad roughness, abrasive size, and abrasive geometry into the formulation to predict the material removal rate. Based on the deformation of hyper-elastic asperities attached to a linear-elastic pad, contact mechanism between the asperities and the wafer is analyzed. Micro-contact mechanism between the particle and wafer is proposed on the basis of elastic-plastic deformation theory. Material removal rate of single abrasive particle is calculated by the abrasive wear theory. The fluid effect in the current model is attributed to the number of active abrasives. Wafer scale material removal rate is analyzed in detail, which is agreed with the experimental results. The Preston’s coefficient, which has been determined empirically, is now given as a function of various processing variables, pad roughness, wafer material properties and slurry status.
Authors: Sung Hyun Kim, Sang Gyun Lee, Seung Geon Choi, Eun Sang Lee, Seung Bok Choi, Chul Hee Lee
Abstract: Electropolishing, the anodic dissolution process without contact with tools, is a surface Treatment method to make a surface planarization using an electrochemical reaction with low current density. Stainless steel can be put various applications which require purity and high precision surface of products. The aim of this study is to investigate the characteristic of electropolishing effect for stainless steel workpieces. In order to analyze the characteristics of electropolishing effect, surface roughness and micro-burr size were measured in terms of machining conditions such as current density, machining time and electrode gap. The tendencies about improvement of surface roughness by electropolishing for stainless steel workpieces were determined.
Authors: Yan Zhao, Wei Cheng, Yuan Wang, Han Chao Gao, Hai Yan Lu
Abstract: A submicron InGaAs/InP DHBT fabricated using triple mesa structure and BCB planarization technology is presented. All processes are on 3-inch wafers. The DHBT with emitter area of 0.7×10μm2 exhibits a current cutoff frequency ft and a maximum oscillation frequency fmax both of 280GHz. The breakdown voltage is more than 4V. The high speed InGaAs/InP DHBT with comparable high breakdown voltage is promising for voltage controlled oscillator (VCO) and mixer applications at W band or even higher frequencies.
Authors: Takeshi Okamoto, Yasuhisa Sano, Kazuma Tachibana, Kenta Arima, Azusa N. Hattori, Keita Yagi, Junji Murata, Shun Sadakuni, Kazuto Yamauchi
Abstract: Catalyst-referred etching (CARE) is an abrasive-free planarization method. We used 3-inch and 2-inch 4H-SiC (0001) 4° off-axis substrates to investigate the processing characteristics that are affected by the substrate diameter. The surface roughness of the 3-inch substrate was extremely smooth over the whole substrate. The surface roughness and removal rate of the 3-inch substrate were approximately the same as those of the 2-inch substrate.
Authors: X. Shen, M. Chang, Ju Long Yuan, Ping Zhao, Wen Hong Zhao, L.B. Zhang
Authors: Takeshi Okamoto, Yasuhisa Sano, Hideyuki Hara, Kenta Arima, Keita Yagi, Junji Murata, Hidekazu Mimura, Kazuto Yamauchi
Abstract: We report a damage-free and efficient planarization process for silicon carbide (SiC) using platinum as a catalyst in hydrofluoric acid (HF) solution. In previous studies, 4H-SiC (0001) on-axis wafers were planarized by this process and an extremely flat surface was obtained. However, electronic device substrates require off-axis wafers. In the present study, 4H-SiC (0001) 8° off-axis Si-face wafers were planarized using a Pt catalyst plate and HF solution. In the first trial using these wafers, the surface roughness worsened and a diagonal pattern was observed by phase-shift interference microscopy. The pattern seemed to have been formed when the Pt plate morphology was transcribed onto the wafer. The removal rate of the 8° off-axis Si-face wafer is much greater than that of the on-axis Si-face wafer. Thus, we concluded that the use of a smoother catalyst plate would be necessary to obtain a smooth 8° off-axis Si-face wafer surface. Improving the Pt plate morphology by hand lapping also improved the surface roughness of the processed wafer as compared with the preprocessed surface. The maximum height of the surface irregularity (peak-to-valley, P-V) and root-mean-square roughness were improved to 0.513 nm and 0.044 nm, respectively, as determined by atomic force microscopy (2×2 μm2).
Authors: Satoshi Takei
Abstract: This study focuses on inorganic gas barrier material in the advanced process techniques of solar cell devices for planarization properties and sublimate defect reduction. The inorganic gas barrier material have been optimized and studied for excellent surface planarization property. The newest approach by excellent collaborations from both process and material has the planarization property on an irregular substrate such as the patterned steps, via and trenches to increase the depth of focus and pattering resolution. A remarkable reduction in via topography with 0.6 μm as a depth and 0.13 μm as a diameter has been achieved excellent thickness bias less than 50 nm in 220 nm blanket field thickness. In addition, the sublimate amount of the film obtained from the developed inorganic gas barrier material was low as compared with that of the film obtained from the referenced organic non-gas barrier material.
Authors: Junji Watanabe, Tohru Hisamatsu, M. Hirano
Authors: J.C. Huang, Yung Jin Weng, Yung Chun Weng, Y.F. Chan, Hsu Kang Liu, H.S. Fang
Abstract: Electrochemical polish technology could enhance the chemo-mechanical polishing efficiency of copper material. During the electrochemical polishing process, both the components and operation parameters of electrochemical polish solution are the key factors influencing planarization ability. This work measured the surface topography and roughness of copper material after mechanical polish by an atomic force microscope (AFM), and added glycerol in different ratios to the phosphoric acid (85 wt %), which was the main composition of experiment solution. Electrochemical polish was conducted within the potential action range in passivation area, and the surface topography and roughness of copper material after electrochemical polish was measured by AFM. The difference in surface topography of copper material after electrochemical polish was compared as well.The experiment indicated that after electrochemical polish in pure phosphoric acid for 50 sec, the surface roughness of copper material obviously decreased from 6.921nm (Ra) to 0.820nm (Ra), and the planarization was more obvious with the increase of electrochemical polish time. The above results could appear in different electrolyte formulas, indicating that electrochemical polish was a good processing method for copper material planarization. This work also proposed the effect of analyzing the electrochemical polish time on planarization through planarization efficiency. Based on the analysis, the planarization efficiency was decreased with the increase of electrochemical polish time, which indicated that longer electrochemical polish time did not yield better result. This work also found that the surface is not only flattened, but also glossed after electrochemical polish.
Authors: Suk Hoon Jeong, Heon Deok Seo, Boum Young Park, Jae Hong Park, Sung Min Park, Sang Chul Kim, Kee Ho Kim, Hae Do Jeong
Abstract: As copper technology moves from pilot to volume manufacturing, semiconductor fabrication is focused on methods to improve device yield. In especially semiconductor manufacturing, electrochemically deposited copper is the material of choice for advanced interconnect applications. Electrochemical deposition (ECD) employs copper plating electrolytes with organic additives to achieve bottom-up filling of small vias and trench with high aspect-ratios. However, for features with small aspect-ratios, the ECD process yields conformal layers because the additives and the bottom-up fill mechanism are not operative in such large features. So, ECD process does not achieve within-die and within-wafer planarity of the deposited copper layer. For planarization of large features and obtaining globally and locally flat films, an electro-chemical mechanical deposition (ECMD) method has been employed. ECMD process is a novel technique that has ability to deposit planar conductive films on non-planar substrate surfaces. Technique involves simultaneous ECD roles and mechanical sweeping of the substrate surface. Copper layer deposited by the ECMD process grows preferentially in cavities on the wafer surface yielding flat profiles and much reduced overburden thickness. Preferential deposition into the cavities on the substrates surface may be achieved through two different mechanisms. The first mechanism is more mechanical in nature and it involves material removal from the top surface. The second mechanism is more chemical in nature and it involves enhancing deposition into the cavities where mechanical sweeping does not reach, and reducing deposition onto surfaces that are swept. Planar layers obtained by the ECMD technique are suitable for low stress material removal processes. Planar layers also yield improved parametric results in device structures after the material removal step. In this study, we demonstrate mechanical role of pad gives effects in ECMD process. So we evaluate gap-filling and planarization between ECMD and ECD.
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