Papers by Keyword: RESURF

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Authors: Seiji Suzuki, Shinsuke Harada, Tsutomu Yatsuo, Ryouji Kosugi, Junji Senzaki, Kenji Fukuda
Authors: W. Wang, S. Banerjee, T. Paul Chow, Ronald J. Gutmann
Authors: S. Banerjee, T. Paul Chow, Ronald J. Gutmann
Authors: S. Banerjee, K. Chatty, T. Paul Chow, Ronald J. Gutmann
Authors: H. Kawano, Tsunenobu Kimoto, Jun Suda, Hiroyuki Matsunami
Abstract: Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.
Authors: Hideto Tamaso, Jiro Shinkai, Takashi Hoshino, Hitoki Tokuda, Kenichi Sawada, Kazuhiro Fujikawa, Takeyoshi Masuda, Satoshi Hatsukawa, Shin Harada, Yasuo Namikawa
Abstract: We fabricated a multi-chip module of 4H-SiC reduced surface field (RESURF)-type lateral JFETs. A single chip consists of 4 unit devices of 2.0 mm × 0.5 mm in size, which were isolated electrically from each other. The multi-chip module consists of 8 chips mounted on an AMC substrate. The drain current and the breakdown voltage of the module are over 3 A and 771 V, respectively. The turn-on time and the turn-off time are 36ns and 166ns, respectively. The module resistance is proportional to the absolute temperature to the 1.05th power.
Authors: J. Spitz, M.R. Melloch, James A. Cooper, Michael A. Capano
Authors: Anant K. Agarwal, N.S. Saks, S.S. Mani, V.S. Hegde, P.A. Sanger
Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: 4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.
Authors: K. Chatty, S. Banerjee, T. Paul Chow, Ronald J. Gutmann
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