Papers by Keyword: Silicon Nanowire

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Authors: Sabar Derita Hutagalung, Kam C. Lew
Abstract: Silicon nanowire transistor (SiNWT) was fabricated by using a silicon nanowire as a channel which directly connected to the source (S) and drain (D). In this work, a side gate (G) formation was used to develop a transistor structure. AFM lithography was performed to create the nanoscale oxide patterns via local anodic oxidation (LAO) mechanism. A conductive AFM tip was used to grow localized oxide layer on the surface of silicon on insulator (SOI) substrate by the application of voltage between tip and substrate. Other parameters that will influence the patterning process such as tip writing speed, relative air humidity, anodization time and substrate orientation were controlled. The patterned structure was etched with tetramethylammonium hydroxide (TMAH) and hydrogen fluoride (HF) acid to remove the uncovered silicon layer and silicon oxide mask patterns, respectively. The surface topography and dimension of the fabricated SiNWT was observed under AFM. Obtained results for the channel thickness, channel length and the distance between the channel and side gate are 32.92 nm, 7.63 µm and 108.07 nm, respectively. Meanwhile, the I-V characteristics of fabricated SiNWT measured at positive gate voltages are similar to p-type FET characteristics.
Authors: Li Shiah Lim, Woo Tae Park, Liang Lou, Han Hua Feng, Pushpapraj Singh
Abstract: Pressure sensors using MEMS technology have been advanced due to their low cost, small size and high sensitivity, which is an advantage for biomedical applications. In this paper,silicon nanowire was proposed to be used as the piezoresistors due to the high sensitivity [1][2].The sensors were designed, and characterized for the use of medical devices for pressure monitoring. The pressure sensor size is 2mm x 2mm with embedded SiNWs of 90nm x150nm been fabricated. Additionally, the sensitivity of 0.0024 Pa-1 pressure sensor has been demonstrated.
Authors: Hui Chiang Teoh, Sabar Derita Hutagalung
Abstract: Silicon nanowires (SiNWs) are important candidate for high performance electronic and optoelectronic devices due to their unique structures, electrical and optical properties. SiNWs were fabricated by silver-assisted electroless etching of Si wafer. Vertically aligned SiNW arrays with length about 8.75 μm and diameter of less than 90 nm have been fabricated. The reflectance of SiNWs without dye (12%) is greatly lower compared to bare Si wafer (25%). Therefore, SiNWs on Si substrate can be used as a good anti-reflection layer for a wide range of incident light. The reflectance of dye-sensitized SiNWs with red, green and blue dyes is 7%, 5.5%, and 5% respectively. The results confirmed that the reflectance of SiNWs with dye is much lower compared to SiNWs without dye and bare Si wafer. It was proven that dye on SiNWs can be used to reduce the reflectance (improved absorption) about 40% compared to SiNWs without dye.
Authors: Ping Yang, Xiang Bo Zeng, Xiao Dong Zhang, Zhan Guo Wang
Abstract: Silicon film as a surface passivation layer is reported to reduce surface recombination on silicon nanowires (SiNWs) and thus enable to improve SiNW solar cell (SC) performance. A question yet to be answered regards the link between the silicon film assets and the solar cell performances. We investigated the effect of the properties of silicon films on the SiNWs SC performances by adjusting hydrogen dilution. Our results showed that the open-circuit voltage (Voc) and short-circuit current density (Jsc) of SiNWs SC increase until hydrogen dilution 10 and then decrease. An open-circuit voltage of 0.397 V and short-circuit current density of 18.42 mA/cm2 are achieved at optimized hydrogen dilution. Based on the analysis of silicon film properties we proposed that the increase of defect density with hydrogen dilution was the main cause for the deterioration of SiNWs SC performance.
Authors: Yan Li Liu, Jian Zhang
Abstract: The effects of different etching temperatures (near room temperature) on the length and surface morphology of SiNWs were reported in this paper. The studies on temperature dependence of SiNWs growth rate were carried out at 20 °C, 30 °C, 40 °C, 50 °C, 60 °C, and 70 °C for n-type and p-type substrates. The results suggested that the SiNWs length could be controlled easily by the change of the etching temperature. Superlong SiNWs were also fabricated by this technique. The superlong SiNWs had the length more than 400 μm and the aspect ratios were about 2000-20000, which could be applied in nanosensors and interconnection.
Authors: Yang He, Cheng Yu Jiang, Heng Xu Yin, Chen Jun, Wei Zheng Yuan
Abstract: A wet etching method for preparing silicon nanowires on silicon substrates at near room temperature is presented. The effect of experiment parameter on the silver nanoparticle forming including concentration of AgNO3, immersing time and solution temperature, and the effect of etching time on the length of silicon nanowires are investigated. It is concluded that solution temperature has more impact to diameter of silicon nanowires than concentration of AgNO3 and immersing time and longer etching time may result in longer silicon nanowires.
Authors: Nor F. Za’bah, Kelvin S.K. Kwa, Anthony O'Neill
Abstract: A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching (ODE) has been developed using <100> Silicon-on Insulator (SOI) as the starting substrate. Initially, the samples were doped with phosphorus using the diffusion process resulting in carrier concentration of 2 x 1018 cm-3. After the silicon nanowires were fabricated, they were measured using a dual configuration method which is similar to the four-point probe measurement technique to deduce its resistivity. The data obtained had suggested that doping distribution in the silicon nanowires were lower and this may have been affected by the surface depletion effect. In addition, with respect to carrier mobility, the effective mobility of electrons extracted using the four-point probe data had demonstrated that the mobility of carriers in the silicon nanowire is comparable with the bulk mobility. This is most probably due to the fact that in this research, the quantum confinement effect on these nanowires is not significant.
Authors: Jia Hong Zhang, Min Yang, Qing Quan Liu, Fang Gu, Min Li, Yi Xian Ge
Abstract: This paper presents a novel and effective characterization method for giant piezoresistive properties of silicon nanowires by using the reference structures. This contrast detection approach investigates the influences of quantum size effect and surface defects effect on piezoresistive coefficients of silicon nanowires by direct comparison of the resistivity change ratio of silicon wires with nanoscale-to-microscale width under the same applied stress conditions. The characterization experiments based on four-point bending tensile test demonstrate that piezoresistive coefficient of small nanowidth silicon nanowire can be significantly increased to about five times higher levels than that of bulk silicon under the same impurity concentration, which indicates that the silicon nanowire can have giant piezoresistive effect. On the other hand, to solve the problem on nanowires pick-up, we proposed a nanowire piezoresistive detection approach, whose validity is confirmed by the dynamic LDV resonance test. Meanwhile, to investigate the influence of undercut arising from the wet chemical release process of the suspended silicon nanowire, a three-dimensional finite element simulation is also carried out for the fundamental resonant frequency using ANSYS software. The numerical and experimental results show that our piezoresistive detection is accurate and effective and the undercut should be carefully considered in the design of the high frequency resonator and mixer. The findings of this paper provide some useful references for the piezoresistive effect measurement and the piezoresistive pick-up in nanoelectromechanical system.
Authors: Mohammad Nuzaihan Md Nor, Uda Hashim, Taib Nazwa, Tijjani Adam
Abstract: A simple method for the fabrication of silicon nanowires using Electron Beam Lithography (EBL) combined with thermal oxidation size reduction method is presented. EBL is used to define the initial silicon nanowires of dimensions approximately 100 nm. Size-reduction method is employed for reaching true nanoscale of dimensions approximately 20 nm. Dry oxidation of silicon is well investigated process for self-limited size-reduction of silicon nanowires. In this paper, successful size reduction of silicon nanowires is presented and surface topography characterizations using Atomic Force Microscopy (AFM) are reported.
Authors: Peng Zhang, Hong Bo Chen, Hong Yu
Abstract: In this article, impact of cross-section and size on vibration of silicon nanowires is simulated by the molecular dynamics method based on molecular dynamics software Material Studio. The comparison of fundamental frequencies of the silicon nanowires with triangle, diamond, and hexagon cross sections is carried out. The orientations of these silicon nanowires are all in <111> direction. Then we change the length and the width of silicon nanowires to investigate the impact of size on vibration of silicon nanowires. The results show that with the influence of surface effect, the vibration frequency of silicon nanowires strongly depends on cross-section and size.
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