Papers by Keyword: SOI

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Authors: P. Dupel, Thierry Chassagne, Didier Chaussende, Yves Monteil, François Cauwet, Etienne Bustarret, A. Deneuville, G. Bentoumi, Eugénie Martinez, B. Daudin, G. Feuillet
Authors: Jian Zhang, Zhao Hua Zhang, Tao Chen, Xiang Ming Kong, Tian Ling Ren, Li Tian Liu
Abstract: TPMS (Tire Pressure Monitoring System) has played a more and more significant role in safely driving nowadays. Low power consumption and excellent accuracy are two of the most important parameters. In this paper, a TPMS with driving status judgment and low-power measurement is designed and realized. A vibration switch is applied to judge the different status of running and stopping. Based on the judgment of driving status, pressure and temperature, different operations will be carried out in order to achieve lower power consumption. The whole system is working intermittently. It has a good performance with a theoretical lifespan of 2 years. The tested communication distance is more than 30m and the resolution is better than 4KPa. A MEMS pressure sensor using SOI wafer with high consistency and accuracy for this TPMS is designed and fabricated. Deep trench etching is adopted to make pressure reference cavity. The ratio of sensitivity variance to its average is 3.5%, which illustrates a good consistency. The total accuracy of the sensor is better than 0.3% and the nonlinearity is less than 0.2%.
Authors: Wei He, Zheng Xuan Zhang
Abstract: A new approach to model the total ionizing dose (TID) induced back channel threshold voltage shift in SOI NMOS transistors was presented. Using a 2D finite element simulation, the trapped charge density in the buried oxide of SOI NMOS resulting from irradiating was analyzed. The model derives from the Radiation-Induced parasitic MOSFET created at the back of the buried oxide . A comparison of the theoretical and experimental results have been obtained for different radiation doses.The agreement between experimental and simulated curves is excellent.
Authors: M. Malak, F. Duport, Hong Cai, B. Saadany, P. Nicole, J.L. Polleux, F. Marty, S. Formont, Ai Qun Liu, Tarik Bourouina
Abstract: This papers deals with the study of novel building blocks suitable for architectures of MEMS tunable lasers integrated in SOI platforms. These building blocks are based on the use of 1D photonic crystals (1D PCs) made of silicon-air thin layers stacks. These provide high reflectivity in certain wavelength range as well as access to simple Fabry-Perot cavities. The latter was studied more in detail and simulations are presented along with preliminary experimental results. A tilted Fabry-Perot cavity was analyzed for its potential of mode selector to prevent for mode hopping and thus enable continuous mode tuning by control of separation gap. As 1D PCs exhibit dispersion characteristics, this behavior is analyzed as well for its potential use for compensation purposes of wavelength dependence of the refractive index in the III-V gain medium.
Authors: Xiang Wei Shen, Xin Zhu Sang, Chong Xiu Yu, Jin Hui Yuan, Cang Jin
Abstract: With the different sizes of the structure parameters of the SOI(Silicon on Insulator) rib waveguide, the dispersion and the nonlinearity parameters are investiaged using the beam propagation method. It is found that for the same structure parameters, the dispersion and the nonlinearity parameter γ are different between the TE and TM modes. With the changing of the structure parameters the anomalous dispersion and the nonlinearity parameter γ can be up to 972 ps/km/nm and 1.065× in the wavelength region near 1550nm.The high anomalous dispersion and the nonlinearity parameter γ means it’s a good candidate to realize parametric amplification and wavelength conversion.
Authors: K. Senthil Kumar, Saptarsi Ghosh, Anup Sarkar, S. Bhattacharya, Subir Kumar Sarkar
Abstract: With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.
Authors: Motoi Nakao, Hirofumi Iikawa, Katsutoshi Izumi, Takashi Yokoyama, Sumio Kobayashi
Abstract: 200 mm wafer with 3C-SiC/SiO2/Si structure has been fabricated using 200 mm siliconon- insulator (SOI) wafer. A top Si layer of 200 mm SOI wafer was thinned down to approximately 5 nm by sacrificial oxidization, and the ultrathin top Si layer was metamorphosed into a 3C-SiC seed layer using a carbonization process. Afterward, an epitaxial SiC layer was grown on the SiC seed layer with ultra-high vacuum chemical vapor deposition. A cross-section transmission electron microscope indicated that a 3C-SiC seed layer was formed directly on the buried oxide layer of 200 mm wafer. The epitaxial SiC layer with an average thickness of approximately 100 nm on the seed was recognized over the entire region of the wafer, although thickness uniformity of the epitaxial SiC layer was not as good as that of SiC seed layer. A transmission electron diffraction image of the epitaxial SiC layer showed a monocrystalline 3C-SiC(100) layer with good crystallinity. These results indicate that our method enables to realize 200 mm SiC wafers.
Authors: Takeshi Hattori, Akira Okamoto, Hitoshi Kuniyasu
Authors: Martin Kittler, Manfred Reiche, Hans Michael Krause
Abstract: The influence of GBs contained in the channel of MOS-FETs - fabricated in thin SOI layers - is demonstrated. The drain current measured at room temperature increases about 50 times for nFETs and about 10 times for pFETs, respectively, as compared to reference devices. The observations might be interpreted as a strong increase of the mobility of charge carriers. Moreover, the observed stepwise changes of the drain current at 5 K may point to Coulomb blockades.
Authors: Jalal Jomaah, Majida Fadlallah, Gerard Ghibaudo
Abstract: A review of recent results concerning the DC characterization of FD- and Double Gate SOI MOSFET’s and FinFETs in modern CMOS technologies is given. By proper extraction techniques, distinction between the different interaction mechanisms is done. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is directly impacted by shrinking the gate length in sub 100nm architectures.
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