Papers by Keyword: Stacking Fault

Paper TitlePage

Authors: Michael Dudley, Yi Chen, Xian Rong Huang, Rong Hui Ma
Abstract: A review is presented of the current understanding of the dislocation configurations observed in PVT-grown 4H- and 6H-SiC boules and CVD-grown 4H-SiC homoepitaxial layers. In both PVT-grown boules and CVD-grown epilayers, dislocation configurations are classified according to whether they are growth dislocations, i.e., formed during growth via the replication of dislocations which thread the moving crystal growth front, or result from deformation processes (under either mechanical or electrical stress) immediately following growth, during post growth cooling, i.e., behind the crystal growth front or during device operation. Possible formation mechanisms of growth defects in the PVT grown boules, such as axial screw dislocations and threading edge dislocation walls are proposed. Similarly, possible origins of growth defect configurations in CVD-grown epilayers, such as Frank faults bounded by Frank partials, BPDs and TEDs, are also discussed. In a similar way, the origins of BPD configurations resulting from relaxation of thermal stresses during post-growth cooling of the PVT boules are discussed. Finally, the susceptibility of BPD configurations replicated into CVD grown epilayers from the substrate towards Recombination Enhanced Dislocation Glide (REDG) is discussed.
Authors: Cheng Lu, Yuan Gao, Hong Tao Zhu, A. Kiet Tieu
Abstract: The defects in crystalline materials significantly affect the fracture behaviors. In this paper molecular dynamics (MD) model using a potential of embedded atom method (EAM) has been developed to investigate the effect of the major crystalline defects, stacking fault and edge dislocation, on the crack propagation in Fe crystal. Six cases with different locations of stacking fault and edge dislocation have been studied. The strain distribution in lattice aggregate was heterogeneous. The dislocations were observed slipping along directions [100] and [-100] on the plane (100). Simulation results showed that the location of the stacking fault and edge dislocation significantly influenced the crack propagation speed.
Authors: Peter J. Wellmann, Desirée Queren, Ralf Müller, Sakwe Aloysius Sakwe, Ulrike Künecke
Abstract: The long term performance of today’s SiC based bipolar power devices suffer strongly from stacking fault formation caused by slip of basal plane dislocations, the latter often originating from the n-type doped SiC substrate wafer. In this paper, using sequentially p-type / n-type / p-type doped SiC crystals, we address the question, whether basal plane dislocation generation and annihilation behaves differently in n-type and p-type SiC. We have found that basal plane dislocations are absent or at least appear significantly less pronounced in p-type doped SiC, which may become of great importance for the stacking fault problem in SiC.
Authors: N. Vouroutzis, Rositza Yakimova, Mikael Syväjärvi, Henrik Jacobsson, J. Stoemenos, Erik Janzén
Authors: Koji Nakayama, Yoshitaka Sugawara, Yoichi Miyanagi, Katsunori Asano, Shuuji Ogata, Shinichi Okada, Toru Izumi, Atsushi Tanaka
Abstract: The behavior of stacking faults with regard to Vf degradations and TEDREC phenomena for 4.5 kV SiCGT have been investigated through the use of light emission images. Stacking faults, which cause Vf degradations, are expanded when current densities are increased. A novel phenomena of Vf degradation reduction, TEDREC phenomena, was found, which can reduce degradation by increasing operating temperature. It was observed for the first time that stacking faults become inactive by elevating temperatures to more than 150 oC in spite of existing stacking faults, which is a factor that contributes to TEDREC phenomena.
Authors: Stanislav I. Soloviev, Peter A. Losee, Stephen Arthur, Zachary Stum, Jerome L. Garrett, Ahmed Elasser
Abstract: Bipolar degradation in 4H-SiC thyristors subjected to high current density stress is reported. The thyristor device structure, its fabrication process as well as testing conditions are described. The Electron Beam Induced Current (EBIC) technique was used for defect analysis in testing of both degraded and non-degraded devices. Possible nucleation sites responsible for the generation of observed defects in degraded devices are discussed
Authors: Michael E. Levinshtein, Pavel A. Ivanov, John W. Palmour, Anant K. Agarwal, Mrinal K. Das
Abstract: We report on specific features of forward voltage degradation of 4H-SiC p-i-n diodes in the pulse mode. It is shown that pulse stresses with a pulse duration shorter than several milliseconds cause substantially smaller forward voltage drift in comparison with a dc stress with the same charge passed through the diodes and the same distribution of injected carriers. A self-recovery of the forward voltage is observed at room temperature.
Authors: Hiromasa Suo, Kazuma Eto, Tomohisa Kato, Kazutoshi Kojima, Hiroshi Osawa, Hajime Okumura
Abstract: The growth of n-type 4H-SiC crystal was performed by physical vapor transport (PVT) growth method by using nitrogen and aluminum (N-Al) co-doping. Resistivity of N-Al co-doped 4H-SiC was as low as 5.8 mΩcm. The dislocation densities of N-Al co-doped substrates were evaluated by synchrotron radiation X-ray topography (SXRT). In addition, epitaxial growth was performed on the N-Al co-doped substrates by chemical vapor deposition (CVD). No double Shockley type stacking fault was observed in the epitaxial layer.
Authors: Hiroyuki Nagasawa, Kuniaki Yagi, Takamitsu Kawahara, Naoki Hatta, Masayuki Abe, Adolf Schöner, Mietek Bakowski, Per Ericsson, Gerhard Pensl
Abstract: In 3C-SiC MOSFETs, planar defects like anti-phase boundaries (APBs) and stacking-faults (SFs) reduce the breakdown voltage and induce leakage current. Although the planar defect density can be reduced by growing 3C-SiC on undulant-Si substrate, specific type of SFs, which expose the Si-face, remains on the (001) surface. Those SFs increase the leakage current in devices made with 3C-SiC. In order to eliminate the residual SFs, an advanced SF reduction method involving polarity conversion and homo-epitaxial growth was developed. This method is called switch-back epitaxy (SBE) and consists of the conversion of the SF surface polarity from Si-face to C-face and following homo-epitaxial growth. The reduction of the SF density in SBE 3C-SiC results in a tremendous improvement of the device performance. The combination of the achieved blocking voltage with the demonstrated high current capability indicates the potential of 3C-SiC vertical MOSFETs for high and medium power electronic applications such as electric and hybrid electric vehicle (EV/HEV) motor drives.
Showing 21 to 30 of 261 Paper Titles