Papers by Keyword: TCAD Simulation

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Authors: Cristina Miccoli, Valeria Cinnera Martino, Salvatore Rinaudo
Abstract: AlGaN/GaN high electron mobility transistors (HEMTs) have shown outstanding improvements in performance and reliability, becoming the leading option for power applications in the 1-40 GHz range. However, the presence of traps and defects in the hetero-structure are strongly correlated to the tolerance of the fabrication process. New powerful models designed to overcome limitations associated with the Process Variability (PV) may be part of the exploitation outcome. This work describes a methodology useful to characterize the effects of PV on AlGaN/GaN HEMTs performance, by deriving Process Compact Model (PCM) from systematic TCAD simulations. The device under examination is an Al0.26Ga0.74N/GaN HEMT and the selected critical process parameters are: molar fraction of the first AlGaN layer, AlGaN layer thickness, source-gate and drain-gate distance, field plate extension, gate height and width, recessed effect under the gate contact.
Authors: Johanna Müting, Bhagyalakshmi Kakarla, Ulrike Grossner
Abstract: The main scattering mechanisms reducing the channel mobility and thus the typical performance of a SiC power MOSFET are reviewed. It is demonstrated that the Poisson equation within the drift-diffusion model is able to account for the effects of ionized impurity scattering. Furthermore, a correlation between the size of macro-or nanosteps at the SiC/SiO2 interface and the corresponding fitting parameter within the Lombardi surface roughness model is established. By qualitatively reproducing the typical performance of a commercial SiC power MOSFET a baseline for the TCAD modeling of power MOSFETs is provided.
Authors: Miguel Hinojosa, Aderinto Ogunniyi, Stephen Bayne, Edward van Brunt, Sei Hyung Ryu
Abstract: This paper presents the current progress in the development of an electro-thermal numerical model for 22 kV 4H-silicon carbide IGBTs. This effort involved the creation of a TCAD model based on doping profiles and structural layers to simulate the steady-state and switching characteristics of recently-fabricated experimental devices. The technical challenge of creating this high voltage SiC IGBT model was incorporating semiconductor equations with sub-models representing carrier mobility, generation, recombination, and lattice heat flow effects with parameters conditioned for 4H-silicon carbide material. Simulations of the steady-state and switching characteristics were performed and later verified with laboratory measurements for an N-type SiC IGBT rated for 22 kV with an active area of 0.37 cm2 and a drift region of 180 μm.
Authors: Dominique Planson, Besar Asllani, Hassan Hamad, Marie Laure Locatelli, Roxana Arvinte, Christophe Raynaud, Pascal Bevilacqua, Luong Viet Phung
Abstract: This paper presents OBIC measurements performed at near breakdown voltage on two devices with different JTE doses. Overcurrent has been measured either at the JTE periphery or at the P+ border. Such overcurrent is present due to the electric field enhancement near the breakdown voltage. This hypothesis is proved by the electroluminescence. TCAD simulation of two different JTE doses yielded similar results to the OBIC measurements.
Authors: Alton B. Horsfall, C. Mark Johnson, Nicolas G. Wright, Anthony G. O'Neill
Authors: Xue Qing Li, Anup Bhalla, Petre Alexandrov
Abstract: This work investigates the short-circuit capability of SiC cascode by performing two-dimensional electro-thermal TCAD simulations. The effects of the threshold voltage of the SiC JFET on the cascode short-circuit withstand time are studied. A design trade-off between the JFET specific-on resistance and the cascode short-circuit withstand time is determined. The experimental results are also presented.
Authors: K. Lee, Benedetto Buono, Martin Domeij, Jimmy Franchi
Abstract: In this work, TCAD modeling of a 1200 V SiC MOSFET is presented. The main focus is on modeling of the channel mobility, and the Coulomb scattering by interface traps and surface roughness are therefore included. For the Coulomb scattering, the interface trap profiles have been extrapolated from the subthreshold characteristics at room temperature, whereas the scattering due to surface roughness has been fitted by comparing to the transfer characteristics at high gate bias. A comparison with measurements for the transfer characteristic and the output characteristic is also presented. Results show that the reduction of the threshold voltage with increasing temperature and the temperature dependence of the output characteristics are properly modeled.
Authors: Min Zhong, Yu Hang Zhao, Shou Mian Chen, Ming Li, Shao Hai Zeng, Wei Zhang
Abstract: An embedded SiGe layer was applied in the source/drain areas (S/D) of a field-effect transistor to boost the performance in the p channels. Raised SiGe S/D plays a critical role in strain engineering. In this study, the relationship between the SiGe overfilling and the enhancement of channel stress was investigated. Systematic technology computer aided design (TCAD) simulations of the SiGe overfill height in a 40 nm PMOS were performed. The simulation results indicate that a moderate SiGe overfilling induces the highest stress in the channel. Corresponding epitaxial growth experiments were done and the obtained experimental data was in good agreement with the simulation results. The effect of the SiGe overfilling is briefly discussed. The results and conclusions presented within this paper might serve as useful references for the optimization of the embedded SiGe stressor for 40 nm logic technology node and beyond.
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