Papers by Keyword: Threshold Voltage Instability

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Authors: Akio Shima, Haruka Shimizu, Yuki Mori, Masakazu Sagawa, Kumiko Konishi, Ryusei Fujita, Takashi Ishigaki, Naoki Tega, Keisuke Kobayashi, Shintaroh Sato, Yasuhiro Shimamoto
Abstract: We investigated improvement ways of to overcome these reliability issues in a 3.3 kV 4H-SiC DMOSFET. JFET doping with (i) narrow width and (ii) deeper depth than that of the p-well region successfully reduced the electric field in the gate insulator and the on-voltage simultaneously. We achieved a low Ron of 26 mΩcm2 at a Vg of +15 V and 150 °C. And highly reliable chips of 0.1 Fit were also achieved both at a positive and negative gate bias of +15 V/ -8 V with MTTF of intrinsic lifetime over 20 years at 3 MV/cm. BTI characterstics both in positive and negative biases also proved reliability over 20 years. The body diode showed stable behavior under forward current operation which is suitable for an external diode-less power module.
Authors: Kevin Matocha, Sujit Banerjee, Kiran Chatty
Abstract: An advanced silicon carbide power MOSFET process was developed and implemented on a high-volume 150mm silicon production line. SiC power MOSFETs fabricated on this 150mm silicon production line were demonstrated with blocking voltage of 1700V with VGS=0V. These SiC MOSFETs have a specific on-resistance as low as 3.1 mΩ-cm2 at room temperature, increasing to 6.7 mΩ-cm2 at 175°C. Devices were packaged in TO-247 package and measured to have on-resistance of 45 mΩ with VGS=20V at room temperature. Clamped inductive switching characterization of these SiC MOSFETs shows turn-off losses as low as 110 uJ (700V, 19.5A). The high-temperature gate bias stability was characterized at positive (+20) and negative gate bias (-10V) at 175°C. After 750 hours of gate stress at a gate bias of VGS=+20V and 175°C, we observe less than a 250mV shift in the threshold voltage. After 750 hours of stress at VGS=-10V and 175°C, we characterize a threshold voltage shift less than 100mV. This shows promise for high-volume production of reliable SiC MOSFETs on 150mm wafers.
Authors: Aivars J. Lelis, Daniel B. Habersat, G. Lopez, J.M. McGarrity, F. Barry McLean, Neil Goldsman
Abstract: We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).
Authors: Daniel Haasmann, Hamid Amini Moghadam, Ji Sheng Han, Amirhossein Aminbeidokhti, Alan Iacopi, Sima Dimitrijev
Abstract: In this paper, we present surprising MOS capacitor C–V bias instability observed in NO-grown oxides, with distinctly different behavior compared to that of conventional NO-annealed oxides on 4H-SiC. Using sequential back-and-forth and bias-temperature stress C–V measurements, it was demonstrated that the C–V shift direction of NO-grown oxides was opposite to that of NO-annealed oxides. A model based on bias-temperature stress orientated near-interfacial dipoles is proposed to explain this unique behavior of NO-grown oxides.
Authors: Mitsuru Sometani, Dai Okamoto, Shinsuke Harada, Hitoshi Ishimori, Shinji Takasu, Tetsuo Hatakeyama, Manabu Takei, Yoshiyuki Yonezawa, Kenji Fukuda, Hajime Okumura
Abstract: In this work, we investigated the methods that measure the threshold voltage (Vth) instability without relaxation of the gate stress during the Vth measurement. We propose a non-relaxation method that demonstrates exact Vth shifts compared with conventional methods that are not as accurate. In the non-relaxation method, the constant gate-source voltage (Vgs) is continuously applied as a gate stress while the drain voltage (Vds) shift required to maintain a constant drain current (Id) is measured. Then, the Vds shift is converted to a Vth shift. The Vth shift values measured by the non-relaxation method are larger than those measured by the other methods, which means that the non-relaxation method can very accurately measure the Vth shift.
Authors: Daniel B. Habersat, Ronald Green, Aivars J. Lelis
Abstract: We reviewed the practical challenges of assessing the threshold voltage drift of SiC MOSFETs in the context of a commercial production environment and qualification standards. Stress bias interruption is a key challenge owing to the rapid recovery of threshold following the removal of bias and the necessity of delays and bias interruptions when qualifying device lots. The test standards in use proscribe how such interruptions should be handled using a re-application of the stress once the device is ready for characterization but these turn out to be completely inadequate when dealing with the trapping mechanics of SiC MOS. Our data indicates that a relatively short stress re-application can be successful at restoring a majority of the threshold voltage drift, scaling with the square root of the interruption time. Additionally, it is important to re-apply the stress bias even for brief interruptions since the threshold recovers so quickly (as opposed to the 96-hour stress interrupt window that is allowed before any re-application is necessary in JESD22 A-108D).
Authors: Katsuhiro Kutsuki, Sachiko Kawaji, Yukihiko Watanabe, Masatoshi Tsujimura, Toru Onishi, Hirokazu Fujiwara, Kensaku Yamamoto, Takashi Kanemura
Abstract: The effect of Al doping concentration (NA) at channel regions ranging from 1.0×1017 to 4.0×1017 cm-3 on the effective channel mobility of electron (μeff) and the threshold voltage (Vth) instability under the positive bias-temperature-stress conditions has been investigated througu the use of trench-gate 4H-SiC MOSFETs with m-face (1-100) channel regions. It was found that μeff degraded with an increase in NA. On the other hand, the increase of NA enlarged the Vth instability. These results indicate that NA has a large impact not only on the Vth value but also on the channel resistance and reliability in 4H-SiC trench MOSFETs.
Authors: Yoshihito Katsu, Takuji Hosoi, Yuichiro Nanen, Tsunenobu Kimoto, Takayoshi Shimura, Heiji Watanabe
Abstract: We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.
Authors: Hiroshi Yano, Tsuyoshi Araoka, Tomoaki Hatayama, Takashi Fuyuki
Abstract: Effects of combination of NO and POCl3 annealing on electrical properties and their stability of 4H-SiC MOS capacitors and MOSFETs were investigated. Channel mobility of MOSFETs processed with both NO and POCl3 annealing did not exceed that of POCl3 annealed MOSFETs. As for the stability of flat-band voltage and threshold voltage using a constant field stress test, the combined annealed sample indicated very stable characteristics compared with single annealed devices with NO or POCl3. The reason for obtaining stable electrical properties is discussed based on nitridation and phosphorization effects at the interface.
Authors: Min Seok Kang, Bong Mook Lee, Veena Misra
Abstract: This study reports the electrical characteristics and reliability of the atomic layer deposited SiO2 on the 4H-SiC substrate. By controlling the thickness of SiO2 in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO2 dielectrics as well as reduction in interface state density at SiC/SiO2 interface.
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