Papers by Keyword: Transconductance

Paper TitlePage

Authors: Seikoh Yoshida, Hirotatsu Ishii, Jiang Li
Authors: Masayuki Yamamoto, Yasunori Tanaka, Tsutomu Yatsuo, Koji Yano
Abstract: We investigate a cascode configuration of a normally-on SiC-Buried Gate Static Induction Transistor (SiC-BGSIT) and Si-MOSFET as an alternative switching device of the SiC-MOSFET. It is shown that the transconductance of our cascode device is much higher than that of commercial SiC-MOSFETs while the switching speed is much faster than that of normally-off SiC-BGSITs. The origin of the fast switching speed in this cascode configuration is discussed in terms of a simulated reverse transfer capacitance.
Authors: Y.Y. Gomeniuk, Y.V. Gomeniuk, A. Nazarov, P.K. Hurley, Karim Cherkaoui, Scott Monaghan, Per Erik Hellström, H.D.B. Gottlob, J. Schubert, J.M.J. Lopes
Abstract: The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.
Authors: K.H. Baik, Seung Joon Ahn, Chul Geun Park, Seung Young Lee, Seung Joon Ahn
Abstract: We investigated the characteristics of the HfO2 layer deposited by ALD method in MOSFET devices where the HfO2 film is incorporated as the gate dielectric layer. The HfO2 film was annealed with forming gas (FG) or high-pressure D2 gas to investigate the effect of annealing on the characteristics of the MOSFET device. It was found that the drain current and transconductance of the D2-annealed MOSFET device increased remarkably by ~10% compared with those of FG-annealed MOSFET device, which is a definite improvement that may contribute to reliable operation of the ultra high-density MOSFET devices.
Authors: Praneet Bhatnagar, Nicolas G. Wright, Alton B. Horsfall, Konstantin Vassilevski, C. Mark Johnson, Michael J. Uren, Keith P. Hilton, A.G. Munday, A.J. Hydes
Abstract: 4H-SiC depletion mode (normally-on) VJFETs were fabricated and characterised at temperatures up to 377 °C. The device current density at drain voltage of 50 V drops down from 54 A/cm2 at room temperature to around 42 A/cm2 at 377 °C which is a 20 % reduction in drain current density. This drop in drain currents is much lower than previously reported values of a 30 % drop in JFETs at high temperatures. The average temperature coefficient of the threshold voltage was found to be -1.36 mV/°C which is smaller than for most Si FETs. We have found that these devices have shown good I-V characteristics upto 377 °C along with being able to retain its characteristics on being retested at room temperature.
Authors: Danupat Duangmalai
Abstract: In this paper, arealizationcurrent controlled current conveyor transconductance amplifier (CCCCTA)is presented astheactiveelement.Thisdesignwas based on aCMOStechnology of AMIS 0.35μm (MOSIS).The PSPICE simulation was used to study the performances of the proposed circuit. It was found that the abilities of differential-pair CCCII circuit and Electronically current-tunable (EOTA) can be achieved using the supply voltages of ±1.5volts and the transconductance gain of the circuit can be linearly tuned.
Authors: Akio Shima, Kikuo Watanabe, Toshiyuki Mine, Naoki Tega, Hirotaka Hamamura, Yasuhiro Shimamoto
Abstract: We investigated the effect of an Al2O3 insertion layer in the gate insulator to make Vth higher and to improve the transconductance Gm in a SiC-MOSFET. Insertion of the Al2O3 layer successfully enlarged Vth by about 4 V. The Vth difference sub-threshold Id-Vg characteristics measured by sweeping the gate voltage bi-directionally indicates that insertion of the Al2O3 layer decreased the number of traps of electrons in the gate insulator. Due to this decrease, device reliability in long-term operation was improveed by smaller Vth shift in PBTI. It was also found that the insertion of the Al2O3 layer improved Gm by two times. Using this gate insulator, we succeeded in fabricating 600 V 20 A-class vertical SiC DMOSFETs with a high Vth (>5 V) and low Ron of 3 mΩcm2.
Authors: Victor Veliadis, Harold Hearne, Ty McNutt, Megan Snook, Paul Potyraj, Charles Scozzie
Abstract: High-voltage vertical-junction-field-effect-transistors (VJFETs) are typically designed normally-on to ensure low-resistance voltage-control operation at high current-gain. To exploit the high-voltage/temperature capabilities of VJFETs in a normally-off voltage-controlled switch, high-voltage normally-on and low-voltage normally-off VJFETs were connected in the cascode configuration. The cascode gate’s threshold voltage decreases from 2.5 V to 2 V as the temperature increases from 25°C to 225°C, while its breakdown voltage increases from -23 V to -19 V. At 300°C, the drain current of the cascode switch is 21.4% of its 25°C value, which agrees well with the reduction of the 4H-SiC electron mobility with temperature. The VJFET based all-SiC cascode switch is normally-off at 300°C, with its threshold voltage shifting from 1.6 V to 0.9 V as the temperature increases from 25°C to 300°C. This agrees well with the measured reduction in VJFET built-in potential. Finally, the reduction in cascode transconductance with temperature follows that of the theoretical 4H-SiC electron mobility. Overall, the measured thermally-induced cascode parameter shifts are in excellent agreement with theory, which signifies fabrication of robust SiC VJFETs for power switching applications.
Showing 1 to 8 of 8 Paper Titles