Papers by Keyword: Underfill

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Authors: Ikuo Shohji, Keisuke Yoshizawa, Masaharu Nishimoto, Takayuki Kawano
Abstract: The effect of the mechanical and physical properties of an underfill material on thermal stress relief in a lead-free chip size package (CSP) solder joint has been investigated. Thin sheets of underfill materials for the CSP solder joint were prepared and the mechanical and physical properties of the sheets were investigated. Using these properties, thermal stress relief in an encapsulated CSP lead-free solder joint with the underfill material was examined by a finite element analysis method under thermal cycle conditions in the temperature range from 293K to 398K and 233K.
Authors: Zainudin Kornain, A. Jalar, Rozaidi Rasid, C.S. Foong, T.L. Wong
Abstract: This paper presents the method to estimate curing profile's parameters for curing process of Moisture Resistance Cyanate Ester (MRCE) based underfill used in Flip Chip Ceramic Ball Grid Array (FC-CBGA). The two steps curing profile was found to eliminate voids formation in underfill during curing process. The important parameters in two steps curing profile such as first fixed temperature and duration of second temperature rise were estimated by superimposed of cure initiation curve and weight percentage loss curve of underfill epoxy material. Differential Scanning Calorimeter (DSC) analysis was carried out to characterize the cure kinetics reaction of underfill epoxy and produced the cure initiation curve. Thermal Gravimetric Analysis (TGA) was performed to characterize the weight loss of underfill and produced the weight loss curve. It was estimated that the first fixed temperature and duration of second temperature rise for two steps curing profile were 100 oC and 60-80 minutes respectively. The simulation experiment was conducted to verify the profile and no voids formation observed along this curing process.
Authors: Mohammad Hafifi Hafiz Ishak, Mohd Zulkifly Abdullah, M.K. Abdullah, A. Abdul Aziz, W.K. Loh, R.C. Ooi, C.K. Ooi
Abstract: Finite volume method (FVM) based simulation of 3D fluid-structure interaction (FSI) of stacked chip package during the encapsulation process of moulded underfill (MUF) in different aspect ratio is presented in this paper. The 3D model of flip chip package is built and meshed using ANSYS ICEM, and simulated by FLUENT software. Castro–Macosko viscosity model and volume of fluid (VOF) technique are applied for flow front tracking of the encapsulant. Curing kinetics is taken into consideration in the simulation using Kamal’s equation. To solve the Castro–Macosko and Kamal models, suitable user defined functions (UDFs) are developed using MS VISUAL STUDIO.NET software and incorporated into the FLUENT. The parameter such as different aspect ratio of stacked die of mold cavity on the flow front behaviour is mainly studied. Mechanical stresses experienced by the silicon die will also be monitored for risk of die cracking. The visualisation of the 3D stacking-chip package encapsulation process was presented at different filling times. The encapsulation model aided a clear visualisation and improved fundamental understanding of the design of a 3D integrated circuit encapsulation. The proposed analysis is expected to be a reference and guide in the design and improvement of 3D integration packages.
Authors: Meng Kao Yeh, C.Y. Tsai
Abstract: The material properties of underfill and substrate in flip chip package have temperature-dependent and moisture-sensitive characteristics. During the solder reflow process, the CTE mismatch in the package causes thermal stresses, which may reduce the reliability of the flip chip package. The package reliability can be improved by varying the die thickness, the fillet angle and the thickness of the underfill and by changing the underfill material. In this paper, the temperature- dependent properties of the underfill were established first. The flip chip reliability was then analyzed by finite element code ANSYS. Both underfill A and underfill B were used in the analysis. The results show that better reliability of the flip chip package was obtained for underfill A, for larger fillet angle of the underfill, for thinner die in the package, and for larger Young's modulus of underfill with linear elastic assumption. Also a hygrothermal preconditioning before thermal cycling reduces the reliability of the flip chip package.
Authors: Dae Gon Kim, Jong Woong Kim, Sang Su Ha, Ja Myeong Koo, Bo In Noh, Seung Boo Jung
Abstract: Thermo-mechanical reliability of the solder bumped flip chip packages having underfill encapsulant was evaluated with thermal shock testing. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu6Sn5 IMC layer, while the two phases which were (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 were formed between the solder and electroless Ni-P layer of the package side. A crack was formed at the upper edge region of solder bump, and propagated through the solder region. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally activated solder fatigue failure. After thermal shocks of 2000 cycles, one more crack which was not observed in the case of non-underfill encapsulated flip chip was observed at the left side of interface between solder bump and substrate. The addition of this crack formation should be due to the underfill encapsulation between the Si chip and substrate.
Authors: Bo In Noh, Seung Boo Jung
Abstract: The thermal fatigue properties of the solder joints with various underfills were evaluated by thermal shock test. Flip chip package with electroless nickel-immersion gold plated on Cu pad of FR-4 substrate and the Sn-37Pb solder ball was used. The thermal fatigue crack initiated at the edges of interface between solder and silicon die. The fatigue property of package with underfill, which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) value was better than that of package with underfill having a lower Tg and higher CTE.
Authors: Bo In Noh, Seung Boo Jung
Abstract: Thermal fatigue properties of solder joints encapsulated with underfill were studied conducting thermal shock tests. Flip chip package with electroless nickel-immersion gold plated on FR-4 substrate and the Sn-3.0Ag-0.5Cu solder ball was used. The fatigue property of package with underfill was better than the package without it. The fatigue property of package with underfill which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) was better than that of package with underfill with lower Tg and higher CTE.
Authors: Zainudin Kornain, Azman Jalar, Rozaidi Rashid, Shahrum Abdullah
Abstract: Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.
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