Papers by Keyword: VJFET

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Authors: Gang Chen, Xiao Feng Song, Song Bai, Li Li, Yun Li, Zheng Chen, Wen Wang
Abstract: A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with lift-off trenched and implanted method. Its blocking voltage exceeds 1300V at gate bias VG = -6V and forward drain current is in excess of 5A at gate bias VG = 3V and drain bias VD = 3V. The SiC VJFET device’s current density is 240A/cm2 at VG= 3V and VD = 3V, with related specific on-resistance 8.9mΩ•cm2. Further analysis reveals that the on-resistance depends greatly on ohmic contact resistance and the bonding spun gold. The specific on-resistance can be further reduced by improving the doping concentration of SiC channel epilayer and the device’s ohmic contact.
824
Authors: Jian Hui Zhao, Kiyoshi Tone, Larry X. Li, Petre Alexandrov, Leonid Fursin, M. Weiner
1213
Authors: Igor Sankin, J. Neil Merrett, W.A. Draper, Janna R. B. Casady, Jeff B. Casady
1249
Authors: Michael S. Mazzola, Jeff B. Casady, Neil Merrett, Igor Sankin, W.A. Draper, D. Seale, V. Bondarenko, Yaroslav Koshka, J. Gafford, R. Kelly
1153
Authors: Dominique Tournier, Phillippe Godignon, Josep Montserrat, Dominique Planson, Jean-Pierre Chante, F. Sarrus
1403
Authors: Rahul Radhakrishnan, Jian Hui Zhao
Abstract: In this paper, we describe the design of a high voltage SiC VJFET monolithically integrated with a JBS diode. The integrated device that was demonstrated up to 834 V in forward blocking doesn’t add any steps to the VJFET fabrication process. While the diode and VJFET share the same surface field termination mechanism, they are partially isolated using implanted field rings. We describe TCAD based optimization of the dimensions of these field rings and outline the design of the JBS diode using a fully analytical 2-D model.
1041
Authors: Andrew Ritenour, Volodymyr Bondarenko, Robin L. Kelley, David C. Sheridan
Abstract: Prototype 800 V, 47 A enhancement-mode SiC VJFETs have been developed for high temperature operation (250 °C). With an active area of 23 mm2 and target threshold voltage of +1.25 V, these devices exhibited a 28 m room temperature on-resistance and excellent blocking characteristics at elevated temperature. With improved device packaging, on-resistance and saturation current values of 15 m and 100 A, respectively, are achievable.
715
Authors: Gang Chen, Song Bai, Ao Liu, Run Hua Huang, Yong Hong Tao, Lin Wang, Yun Li, Zhi Fei Zhao
Abstract: Results are presented for the silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) fabricated based on in-house SiC epitaxial wafer suitable for power devices. We have demonstrated continuous improvement in blocking voltage, forward drain current under high temperature. The SiC VJFET device’s current density is 360 A/cm2 and current is 11 A at VG= 3 V and VD = 2 V, with related specific on-resistance 5.5 mΩ·cm2. The device exceeds 1200 V at gate bias VG = -10V. The current of the SiC VJFET device is 4 A and the reverse voltage is 1200V at the 200 °C high temperature.
1434
Authors: Praneet Bhatnagar, Nicolas G. Wright, Alton B. Horsfall, C. Mark Johnson, Michael J. Uren, Keith P. Hilton, A.G. Munday, A.J. Hydes
Abstract: Silicon Carbide (SiC) power devices are increasingly in demand for operations which require ambient temperature over 300°C. This paper presents circuit applications of normally-on SiC VFETs at temperatures exceeding 300°C. A DC-DC boost converter using a 4H-SiC VJFET and a SiC Schottky Diode was fabricated and operated up to 327°C. A power amplifier achieved a voltage gain of 3.88 at 27°C dropping to 3.16 at 327°C. This 20 % reduction is consistent with the fall in transconductance of the device.
987
Authors: Praneet Bhatnagar, Nicolas G. Wright, Alton B. Horsfall, Konstantin Vassilevski, C. Mark Johnson, Michael J. Uren, Keith P. Hilton, A.G. Munday, A.J. Hydes
Abstract: 4H-SiC depletion mode (normally-on) VJFETs were fabricated and characterised at temperatures up to 377 °C. The device current density at drain voltage of 50 V drops down from 54 A/cm2 at room temperature to around 42 A/cm2 at 377 °C which is a 20 % reduction in drain current density. This drop in drain currents is much lower than previously reported values of a 30 % drop in JFETs at high temperatures. The average temperature coefficient of the threshold voltage was found to be -1.36 mV/°C which is smaller than for most Si FETs. We have found that these devices have shown good I-V characteristics upto 377 °C along with being able to retain its characteristics on being retested at room temperature.
799
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