Papers by Author: Adolf Schöner

Abstract: The electrically active deep levels in a graphene / silicon carbide field effect transistor (FET) were investigated by drain-current deep level transient spectroscopy (I_D-DLTS). An evaluation procedure for I_D-DLTS is developed in order to obtain the activation energy, the capture cross section and the trap concentration. We observed three defect centers corresponding to the intrinsic defects E₁/E₂, E_i and Z₁/Z₂ in n-type 6H-SiC. The determined parameters have been verified by conventional capacitance DLTS.

Abstract: Two kinds of gate oxides, direct thermal oxidation in a nitrous oxide ambient at 1250°C(TGO) and a PECVD oxide followed by a post deposition oxidation in nitrous at 1150°C (DGO) were studied. DGO showed a lower interface trap density and was able to provide a higher current as being implemented in MOSFETs through the improved channel mobility. However the 6.45 MV/cm average breakdown field of DGO is lower than the 10.1 MV/cm breakdown field of TGO. The lower breakdown field, more leaky behavior and the existence of multiple breakdown mechanisms suggest that DGO needs further improvements before it can be used in real applications.

Abstract: SiC lateral MOSFETs with multi-layers epi-channels were studied in this work. The epi-channel with a high concentration n-type epilayer sandwiched by two lightly doped p-type layers showed a maximum field effect mobility of 17 cm²/V.s, improved from 1.53 cm²/V.s of devices without epi-channels. These devices are normally-off with an average threshold voltage of 1.34V.

Abstract: The effect of phosphorus (P) on the electrical properties of the 4H-SiC / SiO₂ interface was investigated. Phosphorus was introduced by surface-near ion implantation with varying ion energy and dose prior to thermal oxidation. Secondary ion mass spectrometry revealed that only part of the implanted P followed the oxidation front to the interface. A negative flatband shift due to residual P in the oxide was found from C-V measurements. Conductance method measurements revealed a significant reduction of density of interface traps D_it with energy E_C - E_it > 0.3 V for P⁺-implanted samples with [P]_interface = 1.5 10¹⁸ cm^-3 in the SiC layer at the interface.

Abstract: A reliable method for reducing the stacking faults (SFs) is demonstrated on the 3C-SiC (001) surface. It is a practical method based on Monte Carlo (MC) simulations of SF propagation during 3C-SiC epitaxial growth, which showed that introducing some discontinuity on the (001) surface enhanced SF reduction. The method is implemented by patterning on the 3C-SiC (001) surface and subsequent homo-epitaxial growth, and this sufficiently reduced the SF density to less than 400 cm^-1. A yield of 97.4 % was estimated for a device-ready area of 10 mm² by statistical measurements of SF density on the entire epitaxial layer surface.

Abstract: The channel mobility in 3C-SiC n-MOSFETs is investigated by current-voltage and Hall-effect measurements. For comparison, these techniques are also applied to 3C-SiC bulk rods. It turns out that the channel mobility depends on the orientation of the crystal and channel length. The observed results are traced back to the influence of Si-terminated stacking faults (Si-SFs), to the resistance of the drain/source contact and to the warping of the wafer caused by the special growth technique.

Abstract: This paper reports on fabrication and modeling of 4H- and 6H-SiC metal-semiconductor-metal (MSM) photodetectors (PDs). MSM PDs have been fabricated on 4H-SiC and 6H-SiC epitaxial layers, and their performance analyzed by MEDICI simulation and measurements. The simulations were also used to optimize the sensitivity by varying the width and spacing of the interdigitated electrodes. The fabricated PDs with 2 µm wide metal electrodes and 3 µm spacing between the electrodes exhibited, under UV illumination, a peak current to dark current ratio of 105 and 104 in 4H-SiC and 6H-SiC, respectively. The measured spectral responsivity of 6H-SiC PDs was higher compared to that of 4H-SiC PDs, with a cutoff at 407 nm compared to 384 nm in 4H-SiC PDs. Also the peak responsivity occurred at a shorter wavelength in 6H material. A high rejection ratio between the photocurrent and dark current was found in both cases. These experimental results were in agreement with simulation.

Abstract: Quantitative efficacies of several methods for stacking fault (SF) reduction are evaluated using Monte Carlo (MC) simulation. SF density on a 3C–SiC {001} surface depends on interactions of adjoining SFs: annihilation between counter pairs of SFs and termination by orthogonal SF pairs. However, SFs are not entirely eliminated when growth occurs on undulant-Si and switch back epitaxy (SBE) due to spontaneous SF collimation that suppresses the annihilation probability of counter SFs. The MC simulation also reveals the efficacy of SF reduction method which includes the growth of 3C–SiC on finite area bounded by side walls. One can theoretically reduce the SF density below 100 cm^-1 on 3C–SiC {001} surface. A practical way for eliminating the SF by termination at side walls is demonstrated, and it clearly exhibits that the SF density can be reduced under 120 cm^-1.

Abstract: 3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

Abstract: Aluminum-based high-k dielectric materials have been studied for their potential use as passivation for SiC devices. Metal-insulator-semiconductor structures were prepared and their dielectric properties were analyzed using capacitance-voltage and current-voltage measurements. Atomic layer deposition was used for the deposition of dielectric layers consisting of AlN with or without a buffer layer of SiO2, and also a stack of alternating AlN and Al2O3 layers. It has been observed that AlN has a polycrystalline structure which provides leakage paths for the current through the grain boundaries. However, adding alternate amorphous layers of Al2O3 prevent this leakage and give better overall dielectric properties. It is also concluded that the breakdown of the dielectric starts from the degradation of the thin interfacial SiO2 layer.