Papers by Author: Claire Therese Richard

Abstract: 3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.

Abstract: This paper summarizes the process development of TiN barrier etching in presence of copper, for a thick copper level in BICMOS technology. In an industrial context, we have chosen to use a SC1 chemistry in a spin etch single wafer tool. The SC1 composition and therefore the pH level allows - the barrier to be etched with no metallic residues, ( if not clear this can be a source for shorts) - control of the selectivity between copper and TiN - control of lateral etching under copper lines, the possible source of open chains by W attack during TiN etch. The electrical results show a robust process according to current specifications, in terms of leakage and via resistance with a fresh chemistry approach. In fact, the recirculation of SC1 is not possible due to substantial concentration changes during processing, high evaporation rate of Ammonia and high decomposition rate of Peroxide in the presence of copper on surface wafer.