Papers by Author: Hirofumi Matsuhata

Abstract: We investigated the effect of the basal plane dislocation (BPD) density in 4H-silicon carbide (SiC) substrates on the forward voltage (V_sd) degradation of body-diodes. Using reflection X-ray topography, the BPD density was automatically estimated from the substrates prior to fabrication of metal–oxide–semiconductor field-effect transistors (MOSFETs). A strong positive correlation was found between the V_sd shift, which was calculated from the difference before and after forward bias stress at 160 A/cm² for ~500 hours, and the BPD density of the substrate. We show that it is possible to predict V_sd shifts from the BPD densities of SiC substrates prior to the fabrication of MOSFETs. In addition, we examined the origin of stacking faults (SFs) as a result of the application of forward bias stress. We presume that SFs are formed by BPDs converted to threading edge dislocations at the epi/sub interface, as well as by BPDs penetrating into the epitaxial layer.

Abstract: Surface defects with scratch-like appearances are often observed locally on 4H-SiC wafers after epitaxial growth. We evaluated such damaged layer which is the cause of local step bunching using Mirror Projection Microscope (MPJ). As a result, MPJ can be detected l damaged layer which could not be detected using Synchrotron X-ray topography, even if these defects are extremely flat surface, no morphology, damaged layer is used to exist on the subsurface region. Thus, MPJ can be detected dislocation loops on the subsurface region of damage, it is effective to elucidate damaged layer of polishing process, MPJ is to be one of the candidates for inspection techniques of the damaged layer at substrate surface.

Abstract: The causes of extrinsic failures in time-dependent dielectric breakdown characteristics of gate oxide on C-face of 4H-SiC are examined by comparing breakdown points of tested gate oxides with the images of X-ray topography and those of differential interference contrast microscopy. We have concluded as follows: (1) surface morphological defects that originate from threading screw dislocations degrade reliability of gate oxides. (2) These surface defects are not necessarily found on every wafer. (3) Crystallographic defects are not killer defects of MOSFET per se.

Abstract: We report our investigation results on triangular-defects formed on 4deg. off 4H-SiC epi- taxial wafers. Triangular-defects that had neither down-falls nor basal-plane dislocations previously reported as origins of triangular-defects at the tips of triangle were investigated by TEM. Our TEM results revealed that foreign materials contamination that were different from well-known down- -falls in size and in composition caused one of the defect formations and abnormal domain forma- tions were implied to occur and thought to relate to defect formations. We also report that several types of microstructure existed in the isosceles of defect during dislocation analyses around triangular-defects by X-ray topography.

Abstract: Defect formation during the early stages of physical vapor transport (PVT) growth of 4H-SiC was investigated using high resolution x-ray diffraction (HRXRD). Characteristic lattice bending behaviors were revealed in the nearby seed crystal regions of grown crystals. The lattice bending was localized in close proximity to the seed/grown crystal interface, and the (0001) basal planes bended convexly toward the growth direction, indicative of the insertion of extra-half planes pointing toward the growth direction during the initial stages of crystal growth. This paper discusses the possible mechanisms of the observed lattice bending and sheds light on the defect formation processes during PVT-growth of 4H-SiC single crystals.

Abstract: The origins of certain types of micrometer-scale surface morphological defects on SiC epitaxial layers are clarified using X-ray topography. Two types of surface morphological defects are commonly observed on Si- and C-face epitaxial layers. Relatively large pits (around 4μm×2μm) originate from threading screw dislocations (TSDs). Relatively small pits (around 1.5μm×1μm) originate from threading edge dislocations (TEDs). The shapes and depths of these surface morphological pits depend on the fabrication history of the epitaxial wafers.

Abstract: SiO2/4H-SiC interfaces are examined by high-resolution transmission electron microscopy (HRTEM), high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM), and spatially resolved electron energy-loss spectroscopy (EELS). HRTEM and HAADF-STEM images of SiO2/4H-SiC interfaces reveal that abrupt interfaces are formed irrespective of the fabrication conditions. Transition regions around the interfaces reported by Zheleva et al. were not observed. Using EELS, profiles of the C/Si and O/Si ratios across an interface were measured. Our measurements did not reveal a C-rich region on the SiC side of the interface, which was reported by Zheleva et al.

Abstract: The authors fabricated pn diodes with Al+ implantation in p-type epitaxial layers, and investigated the influence of the implantation dose on reverse leakage currents. Only in the highest dose with the Al concentration of 2x1020cm-3, more than 90% of the devices showed high leakage currents above 10-4A at the maximum electric field of 3MV/cm. In such devices, almost all of the emissive spots corresponded to threading screw dislocations (TSDs) by the analysis of emission microscopy and X-ray topography. These TSDs were defined as killer defects with the estimated density of 500cm-2 in the case of the highest dose. The emissions were supposed to be due to microplasmas, since the spectra of the emissions were different from those of heat radiation. Condensation of Al atoms, nitrogen atoms and DI defects were excluded as the origin of the emissions by secondary ion mass spectrometry and low temperature photoluminescence analyses.

Abstract: This paper discusses the issues regarding reliability of large-area (up to 25mm2) gate oxide on the C-face of 4H-SiC. We have shown that the TDDB characteristics of large-area gate oxide improved by separating gate oxidation processes into oxide growth by dry-oxidation and successive interface control by anneal in N2O ambient or that by wet-oxidation followed by anneal in H2 ambient. In particular, dry-oxidation followed by anneal in N2O ambient for interface treatment (dry+N2O process) is effective for the suppression of the random failure in TDDB characteristics. The estimated lifetime of gate oxide of less than 9mm2 by the dry+N2O process is six-digits larger than 30 years. In the case of the TDDB characteristics of 25mm2 gate oxide grown by the dry+N2O process, the initial and random failure in TDDB characteristics is dominant. However, even in this case, we have confirmed that the evaluated lifetime of 25mm2 gate oxide is more than 30 years. In order to clarify the mechanism of the degradation of the TDDB characteristics of large-area gate oxide, we examined the effect of the surface defect on the TDDB characteristics by observing the surface of each broken MOS capacitor after the TDDB test. We have found following results. (1) The initial failures in TDDB characteristics are mainly due to surface defects such as “down fall”, “comet”, and “triangular defect”. (2) The footprints of random failure do not correspond to the positions of smaller surface defects such as “bump”. Finally, we have found that the quality of the epitaxial layer affects random failure rate in the TDDB characteristics of large area gate oxide; the random failure in the TDDB characteristics of 25mm2 gate oxide on epitaxial layer grown by a certain epitaxial vendor is almost suppressed. However, the cause of the difference in TDDB characteristics is not identified.

Abstract: The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.