Papers by Author: Jie Zhang

Abstract: In this paper we present results on the growth of low-doped thick epitaxial layers on 4° off-oriented 4H-SiC using a warm-wall multi-wafer CVD system (Aixtron VP2800WW). Statistical data on doping and thickness of 25 μm to 40 μm layer growth show results similar to standard epilayer growth (5-15 μm). Improvements in thickness and doping uniformity as well as the reduction of epitaxial defects has boosted the quality of 25 μm to 40 μm thick epilayers. Laser light scattering measurements resulted in projected device yields with median values of 83% and 96% for 5×5 mm² and 2×2 mm² die size, respectively. This corresponds to a low epitaxial defect density of < 0.75 cm^-2 in 25-40 μm thick epilayers. This paper also presents results of 60 μm to 150 μm thick epitaxial layer growth. Excellent results for doping, thickness and carrier lifetime were achieved. As an example results of a fully loaded 10×100mm run with 150 μm thick epilayers are presented. Wafer-to-wafer doping and thickness values of 3.7 % and 3.4% for sigma/mean were accomplished, respectively. Typical average lifetime values of 5 μs to 6 μs were measured on the 150 μm thick layers without post-epi treatments.

Abstract: Efforts to develop 150 mm 4H SiC bare wafer and epitaxial substrates for power electronic device applications have resulted in quality improvements, such that key metrics match or outperform 100 mm substrates. Total dislocation densities and threading screw dislocation densities measured for 150 mm wafers were ~4100 cm^-2 and ~100 cm^-2, respectively, compared with values of ~5900 cm^-2 and ~300 cm^-2 measured for 100 mm wafers. While median basal plane dislocation counts in 150 mm samples exceed those of the smaller platform, a nearly 45% reduction was realized, resulting in a median density of ~3900 cm^-2. Epilayers grown on 150 mm substrates likewise exhibit quality metrics that are comparable to 100 mm samples, with median thickness and doping sigma/mean values of 1.1% and 4.4%, respectively.

Abstract: This paper presents the current performance of 150mm SiC epitaxy on state-of-the-art 150mm substrates. Excellent on-wafer uniformity has been achieved with mean thickness uniformity at 1.8% and mean doping uniformity at 5.4%. The epilayer surface is smooth across wafer diameter with a typical defect density below 1 cm^-2. Within a run, wafer-to-wafer variation of 0.7 % for thickness and 5% for doping is demonstrated. The mean values of warp and bow after epitaxy are 35 um 15 μm, respectively. The above metrics are critical to enable cost effective production of 150mm SiC epiwafers suited for device fabrication.

Abstract: Dislocation behavior during homo-epitaxy of 4H-SiC on offcut substrates by Chemical Vapor Deposition (CVD) has been studied using Synchrotron X-ray Topography and KOH etching. Studies carried out before and after epilayer growth have revealed that, in some cases, short, edge oriented segments of basal plane dislocation (BPD) inside the substrate can be drawn towards the interface producing screw oriented segments intersecting the growth surface. In other cases, BPD half-loops attached to the substrate surface are forced to glide into the epilayer producing similar screw oriented surface intersections. It is shown that the initial motion of the short edge oriented BPD segments that are drawn from the substrate into the epilayer is caused by thermal stress resulting from radial temperature gradients experienced by the wafer whilst in the epi-chamber. This same stress also causes the initial glide of the surface half-loop into the epilayer and through the advancing epilayer surface. These mobile BPD segments provide screw oriented segments that pierce the advancing epilayer surface that initially replicate as the crystal grows. Once critical thickness is reached, according to the Mathews-Blakeslee model, these screw segments glide sideways under the action of the mismatch stress leaving IDs and HLAs in their wake.

Abstract: Synchrotron X-ray Beam Topography (SWBXT) and KOH etching observations are presented of interfacial dislocations (IDs) and half-loop arrays (HLAs) which can form under certain growth conditions during homoepitaxy of 4H-SiC on off-cut substrates. The HLAs and IDs are observed to form from pairs of opposite sign basal plane dislocations in the substrate which intersect the substrate surface in screw orientation. These dislocations glide in opposite direction in the epilayer once critical thickness has been exceeded. Half-loop arrays are formed at the same time as the screw-type basal plane dislocations (BPDs) side-glide inside the epilayer. From knowledge of the formation mechanism of the HLAs [, if the line of the HLA is extended to intersect the original threading dislocation line direction, then the distance between this intersection point and the ID along the line direction of the original BPD provides a measure of the critical thickness. It is also calculated that the critical thickness in this case is largely determined by the mutual attractive force between the pairs of opposite sign threading BPDs in the substrate. In addition we observed both interfacial dislocations and HLAs generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches.

Abstract: Results are presented for epitaxial SiC layers grown on 100 mm and 150 mm wafers suitable for power devices by CVD using a VP2800WW multi-wafer reactor with 10×100mm and 6×150mm configurations. We have demonstrated continuous improvement in uniformity for thickness and doping, as well as in defect reduction in standard epitaxy on 100 mm wafers. Thickness and doping sigma/mean values of <1.5% and <8%, respectively, could be routinely achieved. Doping and thickness measurements of 30 μm layer growth show results similar to standard epilayer growth. The averaged projected site yields of 80% for 5x5 mm² and of 96% for 2x2 mm² correspond to a low epitaxial defect density of <1 cm="" sup="">-2 in 30μm thick epilayers. Epilayer structures for bipolar devices like PiN diodes and BJTs are shown. The interface regions between nitrogen doped and aluminum doped layers show an abrupt transition of dopant concentration. Wafer quality of 100 mm and 150 mm material is presented as an important base factor for excellent epitaxial layer quality. It is shown that 150 mm substrates exhibit TSD and BPD densities very similar to the 100 mm materials. Site counts for TSDs and BPDs on sample wafers show dislocations densities of 500 cm^-2 and 300 cm^-2, respectively. After CVD process optimization, a thickness uniformity (sigma/mean) of <1.5% and a doping uniformity of <13% was achieved on epitaxial layers on 150mm.

Abstract: Nomarski optical microscopic, KOH etching and synchrotron topographic studies are presented of faint needle-like surface morphological features in 4H-SiC homoepitaxial layers. Grazing incidence synchrotron white beam x-ray topographs show V shaped features which transmission topographs reveal to enclose 1/4[0001] Frank-type stacking faults. Some of these V-shaped features have a tail associated with them and are referred to as Y-shaped defects. Geometric analysis of the size and shape of the V-shaped faults indicates that they are fully contained within the epilayer and appear to be nucleated at the substrate/epilayer interface. Detailed analysis shows that the positions of the V-shaped stacking faults match with the positions of c-axis threading dislocations with Burgers vectors of c or c+a in the substrate and thus appear to result from the deflection of these dislocations onto the basal plane during epilayer growth. Similarly, the Y-shaped defects match well with the substrate surface intersections of c-axis threading dislocations with Burgers vectors of c or c+a in the substrate which were deflected onto the basal plane during substrate growth. Based on the observed morphology of these defect configurations we propose a model for their formation mechanism.

Abstract: This paper reports the progress of the thick epitaxy development at Dow Corning. Epiwafers with thickness of 50 – 100 m have been grown on 4° off-axis 76mm 4H SiC substrates. Smooth surface with RMS roughness below 1nm and defect density down to 2 cm-2 are achieved for 80 - 100 m thick epiwafers. Long carrier lifetime of 2 – 4 s are routinely obtained, and low BPD density in the range of 50 down to below 10 cm-2 is confirmed. High voltage JBS diodes have been successfully fabricated on these wafers with thick epitaxial layers.

Abstract: Improvements in the quality and consistency of 4H-SiC epitaxy wafers are now starting to enable growth of commercial SiC power device applications in areas such as inverters for photo-voltaic systems and power supplies. Recent work has achieved very low epitaxy surface roughness and very low BPD (Basal plane dislocation) in the on 4 degree off-axis substrates. In this paper, we report characterization of the very low BPD epitaxy wafers and a newly observed triangular defect.