Papers by Author: L.H.A. Leunissens

Abstract: The introduction of metal gates and high-k dielectrics in FEOL and porous ULK dielectrics in BEOL presents severe issues [1] and leads to the requirement of new chemistries and processes. A major challenge in cleaning is the removal of photoresist (PR) in both FEOL and BEOL. In current semiconductor device fabrication flow, the photoresist strip process in FEOL is mostly achieved by applying a sequence of plasma ashing followed by a wet-clean step with sulfuric-peroxide mixture (SPM). But in general, ashing leads to strong oxidation or etching of silicon substrate. Hence, several approaches for ashless PR strip have been reported, such as hot SPM [2] and the combination of a pre-treatment using high velocity CO2 aerosol [3].

Abstract: High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.