Papers by Author: Marco Fanciulli

Abstract: Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

Abstract: The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunnelling dielectric. A longer retention time can be achieved by increasing the tunnel oxide thickness. This however implies higher operating voltages and consequently a reduced write/erase speed. Using high-k materials for tunnel and/or gate oxide it is in principle possible to achieve the goal of a low voltage non volatile memory device. The high dielectric constant of these materials allows using thicker tunnel oxide reducing leakage current. Several approaches have been explored to synthesise ordered arrays of ncs in SiO2 but the transfer of these methodologies to the synthesis of 2-d array of ncs in high-k materials is not trivial. In this work we address the material science issues related to the synthesis of metallic and semiconducting ncs in high-k materials using different techniques. A detailed review of the state of the art in the field is presented and further research strategies are suggested.