Papers by Author: Marco Mauceri

Abstract: We report on the growth of bulk 3C-SiC by sublimation on epitaxial seeding layers (3C-SiC/Si) from chemical vapor deposition. We have reached a materials thickness of 0.85 mm and an area of 10.5 cm² which can be enlarged further. The high crystalline quality is characterized by the absence of secondary polytype inclusions and the absence double position grain boundaries.

Abstract: The growth morphology of epitaxial 3C-SiC crystals grown on hexagonal pillars deeply etched into Si (111) substrates is presented. Different growth velocities of side facets let the top crystal facet evolve from hexagonal towards triangular shape during growth. The lateral size and separation between Si pillars determine the onset of fusion between neighboring crystals during growth at a height tailoring of which is crucial to reduce the stacking fault (SF) density of the coalesced surface. Intermediate partial fusion of neighboring crystals is shown as well as a surface of fully coalesced crystals.

Abstract: The stacking faults (SFs) in 3C-SiC epitaxially grown on ridges deeply etched into Si (001) substrates offcut towards [110] were quantitatively analyzed by electron microscopy and X-ray diffraction. A significant reduction of SF density with respect to planar material was observed for the {111} planes parallel to the ridges. The highest SF density was found in the (-1-11) plane. A previously observed defect was identified as twins by electron backscatter diffraction.

Abstract: We have developed and investigated the quasi-bulk crystal growth of 3C-SiC on transferred, high quality, CVD-grown templates using a sublimation sandwich related technique. The seeding layers were removed from the silicon carrier using a solution of hydrogen fluoride, nitric acid and water and glued to a substrate using carbon glue. The transferred layers were used as seeding material to grow high quality, single crystalline, DPBs free 3C-SiC crystals with thicknesses of up to 860 μm and a size of 18 x 20 mm. Analysis of the 3C-SiC layers was carried out using Laue measurement in back-reflecting geometry, Raman spectroscopy and optical microscopy.

Abstract: The heteroepitaxial growth of 3C-SiC on Si (001) and Si (111) substrates deeply patterned at a micron scale by low-pressure chemical vapor deposition is shown to lead to space-filling isolated structures resulting from a mechanism of self-limitation of lateral expansion. Stacking fault densities and wafer bowing may be drastically reduced for optimized pattern geometries.

Abstract: In this work a new epitaxial process on 6 inches has been performed on 2° off-cut substrate. This off-cut will reduce the material loss during substrate preparation from the crystal boule. The thickness and doping uniformity of the samples grown in the LPE reactor PE1O6 is extremely good and the PL map shows a low defects density. The roughness is slightly higher on 2° off-cut and the process window becomes narrower.

Abstract: In this paper we investigate the role of the growth rate (varied by changing the Si/H₂ ratio and using TCS to avoid Si droplet formation) on the surface roughness (R_q), the density of single Shockley stacking faults (SSSF) and 3C-inclusions (i.e. epi-stacking faults, ESF). We find that optimized processes with higher growth rates allow to improve the films in all the considered aspects. This result, together with the reduced cost of growth processes, indicates that high growth rates should always be used to improve the overall quality of 4H-SiC homoepitaxial growths. Furthermore we analyze the connection between surface morphology and density of traps (D_it) at the SiO₂/SiC interface in fabricated MOS devices finding consistent indications that higher surface roughness (step-bunched surfaces) can improve the quality of the interface by reducing the D_it value.

Abstract: In this paper the epitaxial process with chloride precursors has been described. In particular it has been shown that the growth rate can be increased to about 100 μm/h but higher growth rate can be difficult to reach due to the limited surface diffusion at the usual temperature of SiC epitaxy. This process gives several advantages because it gives the opportunity to increase the throughput and consequently to reduce the cost of epitaxy, using new reactor structures, and to reduce several kind of defects (Basal Plane Dislocations, Stacking Faults, Threading Dislocations) and to decrease the surface roughness at the same time.

Abstract: In this paper we study the surface morphology of <11-20> 4° degree off, silicon terminated, 4H Silicon Carbide (4H-SiC) in terms of growth parameters and post growth argon thermal annealing. We find that out-of-equilibrium conditions favor the reduction of the surface roughness. Furthermore, we find preliminary indications that the same growth parameters that lead to the reduction of the surface roughness promote also a reduction of (1,3) and (4,4) stacking faults density.

Abstract: Using several types of surface analysis (Optical profilometers (OP), Atomic Force Microscopies (AFM), Scanning Electron Microscopies (SEM) and cross-sectional high-resolution Transmission Electron Microscopies (TEM)) we analyze the surface morphologies of misoriented 4H silicon carbide after pre-growth hydrogen etching and homo-epitaxial growths. We observed the characteristic self-ordering of nano-facets on any analyzed surface. This nano-faceting, which should not be confused with step bunching, can be considered as a close-to-equilibrium instability, for this reason can be hindered.