Papers by Author: Michael Grieb

Abstract: This paper introduces n-channel normally-off Trench-MOSFETs on 4H-SiC featuring a blocking voltage of 600 V and 1200 V. The Trench-MOSFETs exhibit a specific room temperature on-state resistance R_DS,on of 1.5 mΩ cm² and 2.7 mΩ cm², respectively. It is shown that a further reduction of the R_DS,on by approximately 25 % can be achieved using square-shaped or hexagonal unit cells instead of stripe-shaped unit cells. The Trench-MOSFET switching characteristics using a double pulse setup with a switching current I_sw of 100 A and a switching voltage V_sw of 450 V is presented and discussed. The short turn-off and turn-on times in the range of several ten nanoseconds yield large maximum di_sw/dt and dv_sw/dt values, which enable highly efficient power conversion with low switching losses.

Abstract: Current power MOSFET devices on Silicon Carbide show a limited inversion channel mobility, which can be a result of the expected very high density of interface states near the conduction band . In the current work, the effect of the post implantation annealing temperature, the thermal oxidation and the nitrogen doping of the n-epi layer on the density of these interface traps is investigated using capacity-conductance measurements. Instead of the usage of very high frequencies as used in , in this investigation the measurements were performed in liquid nitrogen to decrease the recharging times of the interface traps.Due to the different processing the samples showed a wide spreading of the inversion channel mobility. The conductance measurements show a characteristic peak caused by the conduction band near interface traps especially for the low temperature measurements. But these traps could not be correlated to the mobility. Instead, a correlation to the nitrogen doping of the epi layer could be observed.

Abstract: This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO₂) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO₂ gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Abstract: This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight enlargement of the trench width along with a considerable increase of the substrate surface roughness. In addition, X-ray photoelectron spectroscopy (XPS) depth profiles indicate an increased carbon atom concentration at the 4H-SiC surface after the high temperature PTA. The non-stoichiometric surface composition affects the quasi-static capacitance-voltage (QSCV) behavior of MOS structures using a deposited gate oxide (GOX). We assume that a sacrificial oxidation directly after the PTA could restore a stoichiometric 4H-SiC surface.

Abstract: This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Abstract: A high inversion channel mobility is a key parameter of normally off Silicon-Carbide MOS field effect power transistors. The mobility is limited by scattering centers at the interface between the semiconductor and the gate-oxide. In this work we investigate the mobility of lateral normally-off MOSFETs with different p-doping concentrations in the channel. Additionally the effect of a shallow counter n-doping at the interface on the mobility was determined and, finally, the properties of interface traps with the charge pumping method were examined. A lower p-doping in the cannel reduces the threshold voltage and increases the mobility simultaneously. A shallow counter n-doping shows a similar effect, but differences in the behavior of the charge pumping current can be observed, indicating that the nitrogen has a significant effect on the electrical properties of the interface, too.

Abstract: In the present work, we studied the influence of the post-implantation annealing temperature on the performance and oxide reliability of lateral 4H-SiC MOSFETs. The maximum field effect mobility of the MOSFETs at 25°C decreases from 22.4cm²/Vs to 17.2cm²/Vs by increasing annealing temperature from 1600°C to 1800°C. Respectively, the measured meantime to failure is about one order of magnitude higher for the 1700°C annealed sample at an applied field of 8.5MV/cm compared to the 1600°C and 1800°C annealed samples.

Abstract: This study focuses on the characterization of silicon dioxide (SiO₂) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (D_IT) of 1_*10¹¹ cm^-2 eV^-1 under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Abstract: In this work we investigate the effect of the aluminum p-well implant annealing process on the electrical properties of lateral 4H-SiC MOSFET transistors. The interface trap concentration was measured by quasi-static capacitive voltage (QSCV) and negative bias stress measurements on MOSFETs. We found that higher annealing temperatures significantly reduce the trap density in the lower bandgap, and as a consequence the threshold voltage drift of the transistor after negative stress is reduced.

Abstract: The suitability of normally-off 4H-SiC MOSFETs for high temperature operation in logic gates is investigated. Fowler-Nordheim analysis shows a lowering of the effective tunneling barrier height at elevated temperatures. Trap assisted tunneling induced by carbon interstitials is proposed as the responsible mechanism. Nevertheless, reliability of MOS devices even at 400°C is excellent with an extrapolated critical field of 2.69MV/cm for a 10 year time to dielectric breakdown. The switching behavior of logic gates is also characterized between 25°C and 400°C. Using these logic gates, a fully integrated edge triggered flip-flop is build and high temperature operation is demonstrated.