Papers by Author: Peder Bergman

Abstract: The deep levels ON₁ and ON_2a/b introduced by oxidation into 4H-SiC are characterized via standard DLTS and via filling pulse dependent DLTS measurements. Separation of the closely spaced ON_2a/b defect is achieved by using a higher resolution correlation function (Gaver-Stehfest 4) and apparent energy level, apparent electron capture cross section and filling pulse measurement derived capture cross sections are given.

Abstract: We report the development of over 100 μm/h growth rate process on 4-inch diameter wafers using chlorinated growth. The optimized growth process has shown extremely smooth epilayers completely free of surface step-bunching with very low surface defect density, high uniformity in thickness and doping and high run to run reproducibility in growth rate, controlled doping and defect density.

Abstract: 10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a V_F of 3.3 V at 100 A/cm² at 25°C, which was decreased to 3.0 V at 300°C.

Abstract: Carrier lifetime and formation of defects have been investigated as a function of growth temperature in n-type 4H-SiC epitaxial layers, grown by horizontal hot-wall CVD. Emphasis has been put on having fixed conditions except for the growth temperature, hence growth rate, doping and epilayer thickness were constant in all epilayers independent of growth temperature. An increasing growth temperature gave higher Z1/2 concentrations along with decreasing carrier lifetime. A correlation between growth temperature and D1 defect was also observed.

Abstract: Carrier lifetime has been studied as a function of C/Si ratio and growth rate during epitaxial growth of n-type 4H-SiC using horizontal hot-wall CVD. Effort has been put on keeping all growth parameters constant with the exception of the parameter that is intended to vary. The carrier lifetime is found to decrease with increasing growth rate and the highest carrier lifetime is found for a C/Si ratio of 1. The surface roughness was correlated with epitaxial growth conditions with AFM analysis.

Abstract: In this report we present homoepitaxial growth of 4H-SiC on the Si-face of nominally on-axis substrates with diameter up to 100 mm in a hot-wall chemical vapor deposition reactor. A comparatively low carrier lifetime has been observed in these layers. Also, local variations in carrier lifetime are different from standard off-cut epilayers. The properties of layers were studied with more focus on charge carrier lifetime and its correlation with starting growth conditions, in-homogeneous surface morphology and different growth mechanisms.

Abstract: We present a comparison between time-resolved carrier lifetime mappings of several samples and integrated near band edge intensity photoluminescence mappings using a pulsed laser. High-injection conditions and as-grown material are used, which generally allow for the assumption of a single exponential decay. The photoluminescence intensity under these circumstances is proportional to the carrier lifetime and the mappings can be used to detect lifetime-influencing defects in epilayers and give an estimate of the carrier lifetime variation over the wafer. Several examples for the defect detection capability of the system are given.

Abstract: In this report we present homoepitaxial growth of 4H-SiC on Si-face, nominally on-axis substrates with diameters up to 76 mm in a hot-wall chemical vapor deposition reactor. A comparatively low carrier lifetime has been observed in these layers; local variations in carrier lifetime are different from standard epilayers on off-cut substrates. The properties of the layers were studied with focus on charge carrier lifetime and its correlation with starting growth conditions, inhomogeneities of surface morphology and different growth mechanisms.

Abstract: We compare two methods for post-growth improvement of bulk carrier lifetime in 4H-SiC: dry oxidations and implantations with either 12C or 14N, followed by high temperature anneals in Ar atmosphere. Application of these techniques to samples cut from the same wafer/epilayer yields 2- to 11-fold lifetime increases, with the implantation/annealing technique shown to give greater maximum lifetimes. The maximum lifetimes reached are ~5μs after 12C implantation at 600°C and annealing in Ar for 180 minutes at 1500°C. Higher temperatures give decreased lifetimes, a result which differs from reports in literature.

Abstract: SiC MESFETs were scaled both laterally and vertically to optimize high frequency and high power performance. Two types of epi-stacks of SiC MESFETs were fabricated and measured. The first type has a doping of 3×1017 cm-3 in the channel and the second type has higher doping (5×1017 cm-3) in the channel. The higher doping allows the channel to be thinner for the same current density and therefore a reduction of the aspect ratio is possible. This could impede short channel effects. For the material with higher channel doping the maximum transconductance is 58 mS/mm. The maximum current gain frequency, fT, and maximum frequency of oscillation, fmax, is 9.8 GHz and 23.9 GHz, and 12.4 GHz and 28.2 GHz for the MESFET with lower doped channel and higher doping, respectively.