Authors: Xiu Mei Xu, Nandi Vrancken, Guy Vereecke, Samuel Suhard, Geoffrey Pourtois, Frank Holsteyns
Abstract: In semiconductor fabrication, pattern collapse of high aspect ratio structures after wet processing is a major problem that could reduce production yield. In this work, several critical issues which limit our understanding of pattern collapse phenomenon are discussed together with some recent results of experiment and modeling. Special efforts have been put to update some of the most recent developments in characterization techniques.
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Authors: Samuel Suhard, A. Moussa, J. Slakkeboorn, F. Beirnaert, I. de Preter, F. Holsteyns
Abstract: Within 3D stacked integrated circuits (3D-SIC), the fabrication of well-defined and solid microbumps is required. These bumps are typically being processed in presence of probing metal such as Al in order to stack functioning dies [1]. As a result of the variety of metals present and the continuous microbump downscaling towards 10 μm, more selective Cu seed etch chemistries are being screened. These Cu seed etch chemistries should be compatible with a variety of metals (Ni, Sn, Al, Co) and generate bumps without undercut and acceptable lateral etch (< 300 nm/side for 20 μm and < 150 nm/side for 10 μm). However the lateral etch specifications were just met for 20 μm [2] and will be more stringent for 10 μm, especially as the lateral etch specification are within the same range as the Cu seed layer thickness (150 nm). Additionally, the current seed etch process is yielding rough bumps (Rs >15 nm) whereas our target is set to be <12 nm in order to guarantee a good electrical contact.
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Authors: Samuel Suhard, Ihsan Simms, Ian H. Brown, Mizota Shogo, Kagawa Koji, Martine Claes, Thibault Buisson, Anne Jourdain, Gerald Beyer, Stefan De Gendt
Abstract: 3D stacked IC (3D-SIC) is one of the main approaches within 3D technologies as it is the most mature and economically viable technology and provides the highest through silicon via density. Enabling 3D SIC requires the modification of standard IC process flows by adding several process modules, such as through silicon via (TSV), wafer bonding and thinning, prior backside processing (e.g. Cu nails exposure), micro bumps formation for the front side and/or the backside and finally stacking to another chips [. Within the 3D-SIC technology developed at IMEC, surface control and preparation by means of wet clean and wet etch are essential steps notably in two key process modules: wafer thinning and micro bump formation.
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Authors: Hua Cui, Martine Claes, Samuel Suhard
Abstract: A novel wet cleaning formulation approach was developed with a TiN etch rate of more than 30 Å/min at room temperature and more than 100 Å/min at 50°C. The chemicals are compatible with Cu and low-k materials, and are suitable for Cu dual damascene interconnect 28 nm and smaller technology node applications. The chemicals offer a route to in situ controlled TiN pullback or even complete removal of the TiN mask during the cleaning process in single wafer tool applications. The chemicals do not contain NH4OH or TMAH and so are very user-friendly.
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Authors: Samuel Suhard, Martine Claes, Yann Civale, Philip Nolmans, Deniz Sabuncuoglu Tezcan, Youssef Travaly
Abstract: NMP is a commonly used solvent for removing positive photoresist in 3D applications, especially in electroplating and (micro-) bumping. However, the negative photoresists are more and more preferred in these applications. Unfortunately, NMP is inefficient for negative photoresist and it is not considered in Europe as an ESH solvent anymore. In this paper a comparative study was carried out in order to identify a solvent that is ESH friendly and a one-size-fits-all solution for stripping negative-tone and thick positive-tone photoresist (2-22 μm) for (micro-) bumping, electroplating and TSV etch applications. The study was performed at tool level.
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Authors: Tae Gon Kim, Quoc Toan Le, Samuel Suhard, Marcel Lux, Guy Vereecke, Martine Claes, Herbert Struyf, Stefan De Gendt, Paul W. Mertens, Marc Heyns
Abstract: Atomic force microscope (AFM) with inclined sample measurement and hydrophobic functionalized AFM probe was used to visualize the sidewall of low-k pattern and allowed to characterize the hydrophobic characteristics on the sidewall after low-k etch. To functionalized the AFM probe, 1H,1H,2H,2H-Perfluorodecyltrichlorosilane (FDTS) as a hydrophobic film was coated on an AFM probe. Because of the magnitude of the phobic-phobic interaction force and the tip forced to make a phase shift. Using this technique the visualization and characterization of the etch residue on the low-k sidewall can be successfully performed. It is shown that the investigation toward an effective chemical clean for the etch residue removal could be applicable.
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