Papers by Author: Seong Min Lee

Abstract: Semiconductor devices are usually formed on a single silicon wafer during a batch processing method. Individual devices are separated from the wafer during the wafer sawing or dicing step. Subsequent packaging processes are then performed on the individual devices, whose edge portions are very susceptible to mechanical damage from the sawing process. Defects formed along device edges due to the dicing saw blade often provide potential sites for serious reliability problems. If the scribing area is reduced, the number of the separated devices from a single wafer increases, which results in productivity improvement. However, the closer the scribing position of the saw blade comes to the active device pattern, the greater possibility of sawing-induced damage to the active pattern is. Thus, this work shows methods to reduce the negative impact of the saw blade while maintaining close proximity of the scribe lines to the IC devices. In particular, this work suggests that a decrease in the size of the diamond particles embedded in the saw blade and in the rotation speed of the saw blade might contribute to the prevention of sawing-induced damage to device patterns.

Abstract: This study examines how the increased density of passivated metallic conductor lines caused by large circuit integration in semiconductor devices influence their reliability during a thermal-cycling test. It was found that a decrease in the size of the trench-shaped space formed between two passivated conductor lines reduces the thermal cycling reliability of the passivation layer (i.e. in this case, consisting of Si3N4). The increased depth of the trenches results in more severe deformation in the surrounding area and brittle fractures in the passivation layer. In particular, the present work indicates that as the ratio of trench depth to trench width increases from 1:1 to 5:1, the number of failures caused by thermal cycling increases up to 2-fold. Numerical calculation also shows that the region of maximum stress is found at the corner of the interface between the flat passivation layer (i.e., the surface without any trenches) and its underlying metallic conductor. In cases where trenches exist, however, the region of maximum stress shifts from the interface corner to the trench corner. Furthermore, the level of the maximum stress was calculated to be lower at the interface corner than the trench corner, by 11%.