Papers by Author: Tatsuhiro Suzuki

Abstract: There is still little consensus regarding why low contact resistivity is achieved when Ni on n-type 4H- and 6H-SiC is annealed at temperatures of more than above 950°C. The objective of this paper is to provide an answer concerning to this question. It is has been reported that even Ni-based contacts formed in the n++ region exhibited a steep reduction of contact resistivity in an annealing temperature range > 900°C. This effect reduction cannot be explained by the carbon vacancy induced donor model (Vc model) proposed by Han and his coworkers [Appl. Phys. Lett., Vol. 79, p. 1816 (2001)]. And, it is clarified that It was observed that the surface of substrates annealed at 1000°C was not covered with not Ni2Si but with a thin layer of NiSi. Finally, a plausible model is proposed that as the result of annealing at higher temperatures, results in the formation of the a NiSi/SiC system is builtat the substrate interface, resulting in significant reduction in low causing contact resistivity to be reduced significantly.

Abstract: It is strongly desired to operate SiC power devices at higher junction temperatures (Tj), but that often entails problems because they contain a variety of materials with thermal activity or weakness. An example of such troubles is the steep increase in resistance of the Al electrode in the source (or emitter) contact holes, caused by electromigration (EM). In this work, EM reliability of the contact hole in SiC power devices was evaluated for an improved Al electrode sandwiched between thin TaN layers. An estimated mean time to failure (MTTF) of approximately 3400 years was achieved under conditions of Tj = 300°C and J = 104 A/cm2.

Abstract: It was experimentally shown that an ONO gate dielectric carefully formed on 4H-SiC has extremely high reliability even under a negative electric field at least up to a junction temperature of 300°C, making it promising for power MOS and CMOS applications. Medium charge to failure of –30 C/cm2 was achieved for fully processed polycrystalline Si gate MONOS capacitors with an equivalent SiO2 thickness of teq = 44 nm and a 200-μm diameter. The medium time to failure of these capacitors projected for –3 MV/cm exceeds 86 and 6.3 thousand years at room temperature and 300°C, respectively. A parasitic memory action did not appear even when Eox of -6.6 MV/cm was applied for 5000 seconds.

Abstract: This paper discusses critical reliability issues and their countermeasures for vertically structured poly-Si gate n-channel power MOSFETs (DMOS) on 4H-SiC when operated at an elevated temperature of more than 300°C for a long period of time. Two destructive failures were identified in a storage life test at 500°C: a short-circuit between the source and the gate and a disconnection at the n+ source contact. The former was caused by interlayer dielectric erosion and/or Al spearing into the poly-Si gate; the latter was caused by the disappearance of the NiSix contact layer. Effective and practical countermeasures were devised and implemented. Device lifetime against the three different failure mechanisms was improved in every case by at least one order of magnitude.