Papers by Author: Tetsuo Hatakeyama

Abstract: A simple and practical method of characterizing traps at SiC/SiO₂ interfaces close to the bottom of the conduction band by using the split C−V and Hall measurements is proposed. This technique was applied to the characterization of traps at a wet-oxidized SiC/SiO₂ interface on C-face and those at an oxynitrided SiC/SiO₂ interface on Si-face. It was shown that the density of traps near the conduction band of the oxynitrided SiC/SiO₂ interface was more than 10 times larger than that of the wet-oxidized SiC/SiO₂ interface.

Abstract: In this work, we investigated the methods that measure the threshold voltage (V_th) instability without relaxation of the gate stress during the V_th measurement. We propose a non-relaxation method that demonstrates exact V_th shifts compared with conventional methods that are not as accurate. In the non-relaxation method, the constant gate-source voltage (V_gs) is continuously applied as a gate stress while the drain voltage (V_ds) shift required to maintain a constant drain current (I_d) is measured. Then, the V_ds shift is converted to a V_th shift. The V_th shift values measured by the non-relaxation method are larger than those measured by the other methods, which means that the non-relaxation method can very accurately measure the V_th shift.

Abstract: The conduction mechanism of the leakage current in thermal oxide on 4H-SiC was identified. The carrier separation current-voltage method clarified that electrons are the dominant carriers of the leakage current. The temperature dependence of the currentvoltage characteristics indicated that the conduction mechanism of the leakage current involved not only Fowler-Nordheim tunneling (FN) but also Poole-Frenkel (PF) emission. The PF emission current due to the existence of defects in the oxide increased with temperature.

Abstract: Constant-capacitance deep-level transient spectroscopy was carried out to characterize in detail interface states close to the conduction band edge in SiO₂/SiC structures. The measured results are summarized as follows: (1) The capture of electrons by the interface states proceeds logarithmically with time. (2) The emission of electrons accelerates slightly with increasing density of captured electrons. The oxide trap model explains the logarithmic change in capture with time but not the phenomenon of accelerated emissions. This prompted us to formulate a new model that replicates the logarithmic capture process with time. In this model, we postulated the electron density at the interface decreases exponentially as the trapped electron density increases owing to the interaction between the trapped electrons and the free electrons. In this case, the capture process is almost the same as with the oxide trap model except for the definition of parameters. Further, we do not need to take into account the delay of the emission process caused by tunneling. The phenomenon of accelerated emissions may be explained by interactions among captured electrons in this model.

Abstract: Constant-capacitance deep-level-transient spectroscopy (CCDLTS) characterization of traps (or states) in SiO₂/SiC interfaces on the C-face was carried out to clarify the cause of low-channel mobility of SiC MOSFETs. CCDLTS measurements showed that the interface-state density (D_it) near the conduction band of SiO₂/SiC interfaces fabricated using N₂O oxidation was much higher than that of SiO₂/SiC interfaces fabricated using wet oxidation. The high density of interface states near the conduction band is likely to be the main cause of the low mobility of MOSFETs fabricated using N₂O oxidation.

Abstract: The causes of extrinsic failures in time-dependent dielectric breakdown characteristics of gate oxide on C-face of 4H-SiC are examined by comparing breakdown points of tested gate oxides with the images of X-ray topography and those of differential interference contrast microscopy. We have concluded as follows: (1) surface morphological defects that originate from threading screw dislocations degrade reliability of gate oxides. (2) These surface defects are not necessarily found on every wafer. (3) Crystallographic defects are not killer defects of MOSFET per se.

Abstract: The impact of device concepts of Si insulated gate bipolar transistors (IGBTs) such as injection-enhanced IGBT (IEGT), high-conductivity IGBT (HiGT), and Si-limit IGBT on the performance of SiC IGBTs is examined. We first show that the forward characteristics of the original type of planer SiC IGBTs are much worse than those of SiC PiN diodes, even if the carrier lifetime is improved. Next, we show that the forward characteristics of SiC IEGTs and SiC HiGTs are comparable to those of SiC PiN diodes. Thus, device concepts of Si IGBTs are effective in improving the device performance of SiC IGBTs. Finally, it is shown that a SiC-limit IGBT can be realized when the mesa width is less than 0.5 μm.

Abstract: The origins of certain types of micrometer-scale surface morphological defects on SiC epitaxial layers are clarified using X-ray topography. Two types of surface morphological defects are commonly observed on Si- and C-face epitaxial layers. Relatively large pits (around 4μm×2μm) originate from threading screw dislocations (TSDs). Relatively small pits (around 1.5μm×1μm) originate from threading edge dislocations (TEDs). The shapes and depths of these surface morphological pits depend on the fabrication history of the epitaxial wafers.

Abstract: This paper discusses the issues regarding reliability of large-area (up to 25mm2) gate oxide on the C-face of 4H-SiC. We have shown that the TDDB characteristics of large-area gate oxide improved by separating gate oxidation processes into oxide growth by dry-oxidation and successive interface control by anneal in N2O ambient or that by wet-oxidation followed by anneal in H2 ambient. In particular, dry-oxidation followed by anneal in N2O ambient for interface treatment (dry+N2O process) is effective for the suppression of the random failure in TDDB characteristics. The estimated lifetime of gate oxide of less than 9mm2 by the dry+N2O process is six-digits larger than 30 years. In the case of the TDDB characteristics of 25mm2 gate oxide grown by the dry+N2O process, the initial and random failure in TDDB characteristics is dominant. However, even in this case, we have confirmed that the evaluated lifetime of 25mm2 gate oxide is more than 30 years. In order to clarify the mechanism of the degradation of the TDDB characteristics of large-area gate oxide, we examined the effect of the surface defect on the TDDB characteristics by observing the surface of each broken MOS capacitor after the TDDB test. We have found following results. (1) The initial failures in TDDB characteristics are mainly due to surface defects such as “down fall”, “comet”, and “triangular defect”. (2) The footprints of random failure do not correspond to the positions of smaller surface defects such as “bump”. Finally, we have found that the quality of the epitaxial layer affects random failure rate in the TDDB characteristics of large area gate oxide; the random failure in the TDDB characteristics of 25mm2 gate oxide on epitaxial layer grown by a certain epitaxial vendor is almost suppressed. However, the cause of the difference in TDDB characteristics is not identified.

Abstract: The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.