Papers by Author: Twan Bearda

Abstract: In future, thin wafers (< 100µm) will be employed in silicon heterojunction solar cell to decrease modules cost-per-Watt-Peak. However, in order to maintain excellent cell efficiency a higher device surface/volume ratio will demand stricter requirements on surface passivation. In this frame, the status of the crystalline surface (c-Si) prior to amorphous silicon (a-Si:H(i)) plasma deposition (PECVD) plays an important role: the c-Si chemical termination influences the quality of the interface layer a-Si:H(i)/c-Si, and affect the open circuit voltage (V_oc). Previous studies have shown that smooth and fully hydrogenated c-Si surface [ lead to best quality heterojunction. These surfaces can be obtained by different wet cleaning procedures, usually terminated by an immersion in diluted HF. However, after this step, the wafer surface is highly reactive and can re-oxidize rapidly: contaminants presents in air can be adsorbed and affect wafer passivation [. For this reason, in-situ Hydrogen (H₂) plasma cleaning prior to a-Si:H(i) deposition might be an interesting option to decrease the amount of contaminant on the surface. However, the experimental window is extremely narrow, since phenomena like epitaxial growth and ion-bombardment damage can easily occur [[ and worsen the surface passivation operated by a-Si:H(i) layers. In this contribution, we present an in-situ H₂ plasma clean and show a decrease of Oxygen and Carbon on wafer surface after a short time (<10 sec), without detrimental effects on the subsequent passivation.

Abstract: Thermal atomic layer deposition (ALD) of Al2O3 provides an adequate level of surface passivation for both p-type and n-type Si solar cells. To obtain the most qualitative and uniform surface passivation advanced cleaning development is required. The studied pre-deposition treatments include an HF (Si-H) or oxidizing (Si-OH) last step and finish with simple hot-air drying or more sophisticated Marangoni drying. To examine the quality and uniformity of surface passivation - after cleaning and Al2O3 deposition - carrier density imaging (CDI) and quasi-steady-state photo-conductance (QSSPC) are applied. A hydrophilic surface clean that leads to improved surface passivation level is found. Si-H starting surfaces lead to equivalent passivation quality but worse passivation uniformity. The hydrophilic surface clean is preferred because it is thermodynamically stable, enables higher and more uniform ALD growth and consequently exhibits better surface passivation uniformity.

Abstract: Solar cells employing heterojunction emitters of amorphous silicon (a-Si) on a monocrystalline silicon (c-Si) substrate have demonstrated high efficiencies without requiring high-temperature processing [. An example of such a cell structure is shown in Figure 1. It has been found that the cell efficiency can be boosted by inserting a thin undoped (intrinsic) a-Si layer between the a-Si emitter and the c-Si substrate. The thin intrinsic layer provides very good passivation of interface defects, thus reducing the surface recombination velocity.

Abstract: In FEOL processing, doping of active areas like source, drain, and extensions (NMOS and PMOS) is done by ion implantation. Un-doped regions are covered with photoresist to protect them from implantation. Ion implantation modifies the surface of the photoresist to generate a dehydrogenated amorphous carbon layer, the crust [1]. When the implant conditions are more aggressive (higher implant energy and implant dose), the hard crust becomes more and more challenging to be removed [2]. Conventionally, a plasma ashing process followed by a wet cleaning, typically SPM (Sulfuric acid/Hydrogen peroxide mixture) chemistry, can remove the implanted photoresist, but usually leads to damage and strong oxidation of the underlying semiconductor material and hence result in material or dopant loss. As the technology node migrates beyond 45nm, the photoresist removal process should also be compatible with novel materials such as high-k dielectric and metal-gate used in advanced gate stack integration. For these reasons, it is desirable to eliminate the plasma ash and SPM clean chemistry. Wet only PR removal process is studied using new chemistries like solvents that are compatible with the other FEOL process steps, however, the photoresist removal using solvents only still showed lower removal efficiency than conventional processes. It has been demonstrated that the CO2 cryogenic pre-treatment can improve the ion implanted photoresist stripping efficiency of the wet cleaning processes [3], and can also enhance the photoresist removal efficiency by the solvents.

Abstract: Nanostructures with high aspect ratios, HAR, (ratio of height to lateral feature size) are of interest for many applications. One of the immediate advantages is the large surface area of these structures. In the field of DRAM manufacturing for example, the capacitance of cylindrical DRAM capacitors increases linearly with height. Wet etching and drying of these fragile high aspect ratio structures without lateral collapse (stiction) is a big challenge for the fabrication of DRAM capacitors. The problem with HAR structures is stiction during drying [1]. In order to reduce stiction by improvement of drying techniques, a good metric to quantify the occurrence of stiction is needed. However, currently used methods like SEM or brightfield defect inspection are extremely time-consuming.

Abstract: In many process steps of integrated circuits (IC’s) fabrication, silicon wafers are coming in contact with process liquids such as ultra pure water (UPW) and aqueous and non-aqueous chemical mixtures. During these process steps, liquid-borne particle contamination can deposit on the wafer surface. Particle contamination from UPW is an important factor influencing random yield loss of IC’s [ ]. A number of yield models are used to predict yields including Poisson, Murphy, Seeds, and negative binomial models [ , ]. However, these models are based on the assumption that particles are randomly deposited on the wafer surface [ ].

Abstract: High velocity aerosol cleaning using ultrapure water or dilute aqueous solutions (e.g. dilute ammonia) is common in semiconductor IC fabrication [1]. This process combines droplet impact forces with continuous liquid flow for improved cleaning efficiency of sub-100nm particles. As with any physically enhanced cleaning process, improved particle removal can be accompanied by increased substrate damage, especially to smaller (<80nm) features [2]. Solvents such as N-methylpyrrolidone (NMP) and tetrahydrofurfuryl alcohol (THFA) are used for resist strip applications [3]. It is possible, and sometimes useful, to deliver these solvents through the same spray nozzle normally used for aqueous spray cleaning. In this presentation we explore the particle removal and substrate damage performance of 2-ethoxyethanol (EGEE), NMP and THFA as used in a conventional aerosol spray cleaning system

Abstract: As the dimensions of the structures of integrated circuits shrink, the influence of particles on device yield becomes increasingly important. According to the cleaning requirements of the International Technology Roadmap for Semiconductors (ITRS) in 2007, particles of 32 nm and larger are believed to be detrimental to devices and thus have to be removed. To remove nano-particles with minimal substrate loss and no damage requires very dilute chemistries and sufficiently gentle physical forces in a cleaning process. In this work the performance of an aerosol spray based cleaning technique is evaluated with regard to the removal efficiency of nano-particles as well as substrate loss and structural damage.

Abstract: The local particle removal efficiency (PRE) of nano particles in megasonic cleaning experiments is studied. This approach makes it possible to quantify non uniform cleaning effects over the wafer and to look into the dynamics of particle removal at different areas on the wafer. A direct correlation between PRE and megasonic induced damage of device structures demonstrates that a considerable amount of damage is already formed at less efficiently cleaned areas of the wafer.