Papers by Author: Yuuki Ishida

Abstract: The in situ cleaning process of a silicon carbide epitaxial reactor was developed using chlorine trifluoride gas for removing the film-type silicon carbide deposition formed on a susceptor. By adjusting the etching temperature to less than 330 °C, the formed silicon carbide films could be removed without significant damage to the susceptor.

Abstract: Thick multi-layer 4H-SiC epitaxial growth was investigated for very high-voltage Si-face p-channel insulated gate bipolar transistors (p-IGBTs). The multi-layer included n⁺ buffer, p⁺ field stop, and thick p^- drift layers. Two processes were employed to enhance the carrier lifetime of the p^- drift layer: carbon ion implantation/annealing and hydrogen annealing, and the enhanced carrier lifetime was confirmed by the open-circuit voltage decay measurement. Using the grown thick multi-layer 4H-SiC, simple pin diodes were fabricated instead of p-IGBTs to demonstrate efficient conductivity modulation in the thick p^- drift layer. While the on-state voltage was high at room temperature, it decreased significantly at elevated temperatures, and attained 3.5 V at 100 A/cm² at 200°C for the diode with the carrier lifetime enhancement processes, indicating sufficient conductivity modulation.

Abstract: The silicon carbide CVD reactor cleaning process was studied by means of detaching silicon carbide particles, which was formed on the silicon carbide coated carbon susceptor surface during the silicon carbide film deposition. The contact points between the particles and the susceptor surface were etched using chlorine trifluoride gas at temperatures lower than 290 °C for 120 min. During this process, the carbon susceptor covered with the silicon carbide coating film suffered from little damage while achieving cleaning.

Abstract: We have developed the computer simulation including cluster effect and Schwoebel effect and investigated the conditions generating GSB using the simulation. We have demonstrated that the simulation developed can reproduce GSB. We have found for the occurence of GSB that there exists a threshold value of the surplus flux rate of Si-or C-source gases not contributing to growth, which depends on the flux rate of each source gas, namely the boundary between with and without GSB. It is noted that this boundary does not depend on the off-angle of substrates. We have also found the mechanism for explaining the occurrence of wavy surface morphplogy.

Abstract: Trapezoid-shape (T-S) defects on epilayer surfaces, which include two kinds of the giant step bunching (GSB), are one of killer defects for MOSFETs. We have investigated the generation mechanism of the two GSBs using "step kinetics simulator" we developed. The simulator has reproduced the behavior of the GSBs. Based on results from the simulation, we have discussed the generation mechanism of the two GSBs.

Abstract: The defect evolution on 90 μm-thick heavily Al-doped 4H-SiC epilayers with Al doping level higher than 10²⁰ cm^-3 was studied by tracing back to initial growth stage to monitor major dislocations and their propagations in each growth stage. Results from X-ray topography and KOH etching demonstrate that all existing dislocations on the surface of 90 μm-thick epilayer can be identified as the defects originating from substrate. In other words, there seems no new dislocation generated after a long-term growth. Nevertheless, a high density of misfit dislocation was found appearing near the substrate/epilayer interface for epilayer with Al doping level of 3.5×10²⁰ cm^-3, while misfit dislocation cannot be seen on epilayer with Al doping level of 1.5×10²⁰ cm^-3.

Abstract: The epitaxial growth of thick multi-layer 4H-SiC to fabricate very high-voltage C-face n-channel IGBTs is demonstrated using 3-inch diameter wafers. We employ an inverted-growth process, which enables the on-state voltage of resultant IGBTs to be reduced. Furthermore a long minority carrier lifetime (> 10 μs) and a low-resistance p⁺ epilayer can reduce the forward voltage drop of the IGBTs. The small forward voltage drop is demonstrated particularly at high temperatures by fabricating and characterizing simple pin diodes using the epi-wafer.

Abstract: By using hot-wall CVD method, thick heavily Al-doped 4H-SiC epilayers (~90 μm) were grown on 3-inches 4H-SiC wafers. Around the solubility limit, the incorporation behaviors of Al into 4H-SiC were investigated by varying the growth conditions. Among the samples having smooth surfaces, the maximum Al dopants concentration of 3.5×10²⁰ cm^-3 and the minimum resistivity of 16.5 mΩcm were achieved. The results of Hall-effect measurement demonstrate that, along with the increase of Al doping level, the activation ratio of Al dopants gradually increases from several percent up to 100% where the Al dopants concentration is 1.5×10²⁰ cm^-3.

Abstract: The surface and interface roughness of SiO₂/4H-SiC(0001) was investigated in terms of Si emission from the interface and oxidation induced compressive stress. It was demonstrated that the SiO₂ surface roughness growth was strongly related with oxidation mechanism, as well as SiO₂ on Si substrate. A model for surface roughening was proposed with areal Si density and Young’s modulus to inclusively explain the surface roughness of SiO₂ on various substrates.

Abstract: In this study, we investigated the cluster effect on the occurrence of giant step bunching. We generated carbon clusters on 4H-SiC (0001) surfaces by thermal decomposition of SiC in an Ar atmosphere and controlled the surface concentrations of the clusters by adding H2 gas. We found the boundaries between surfaces with and without giant steps to show Arrhenius-type behavior. This behavior agreed with our predictions deduced from a chemical reaction model that takes the cluster effect into account, suggesting that giant step bunching is attributable to the formation of clusters on SiC.